Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-04-19
2009-12-08
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S734000, C365S201000
Reexamination Certificate
active
07631231
ABSTRACT:
In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan cell connected to each bond pad, allowing for rapid connectivity testing of flash memory chips in accordance with testing standards such as the JTAG standard. The invention further includes methods in which the pins and/or memory cells of a flash memory chip are sequentially sent a series of data so as to test the connectivity of portions of the IC. The sequentially-sent data is then retrieved and compared to the original data. Discrepancies between these sets of data thus highlight connectivity problems in the IC.
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“Memory system connectivity exploration” by Grun et al. Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings Publication Date: 2002 On pp. 894-901 ISBN: 0-7695-1471-5.
Klotzkin Phil
Nguyen Hung O.
Nguyen Sang Thanh
Tran Hieu Van
Britt Cynthia
DLA Piper (LLP) US
Silicon Storage Technology, Inc.
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