Method and apparatus for testing random access memory devices

Details Method and apparatus for testing random access memory devices Method and apparatus for testing random access memory devices

1998-10-30

2000-01-25

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

365200, G11C 700

Patent

active

060184841

ABSTRACT:
A method and apparatus for testing a random access memory device, such as a dynamic random access memory device embedded within an integrated circuit chip. The apparatus includes one or more rows of transistors, each of which is connected to a bit line pair of the memory device and to a data line. Data is placed onto the bit lines by driving the data line to a predetermined voltage level and turning on the transistors in the transistor row. Data placed on the bit lines forms a test pattern that may be subsequently written into any row of memory cells. By directly controlling the bit lines of the memory device in this way, test patterns may be quickly and easily stored in the memory device for functional verification thereof.

REFERENCES:
patent: 4868823 (1989-09-01), White, Jr. et al.
patent: 5305261 (1994-04-01), Furutani et al.
patent: 5455798 (1995-10-01), McClure

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