Method and apparatus for testing quiescent current in integrated

Electronic digital logic circuitry – Tri-state – With field-effect transistor

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326 16, 326121, H03K 190948, H03K 1900

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active

059398973

ABSTRACT:
A method and apparatus for obtaining near 100 percent quiescent current test coverage within a reasonable amount of time is accomplished by providing a plurality of test circuits interdisposed between a plurality of combinational logic circuits. During testing, the testing circuits isolate the input of one combinational logic circuit from the output of the preceding combinational logic, thus allowing the test circuit to stimulate the input of the combinational logic circuit. By performing the input stimulations of the plurality of combinational logic circuits simultaneously, only two test steps are needed to check the quiescent current of the plurality of combinational logic circuits.

REFERENCES:
patent: 5329175 (1994-07-01), Peterson

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