Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-03-29
2004-01-20
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S189020, C365S230030, C365S233100, C326S038000, C326S040000, C326S041000
Reexamination Certificate
active
06680871
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a mask-programmable logic device having embedded random access memory blocks. More particularly, the invention relates to such a device having circuitry for testing the random access memory blocks, and to a method of testing.
Programmable logic devices are well known. Early programmable logic devices were one-time configurable. For example, configuration may have been achieved by “blowing”—i.e., opening—fusible links. Alternatively, the configuration may have been stored in a programmable read-only memory. These devices generally provided the user with the ability to configure the devices for “sum-of-products” (or “P-TERM”) logic operations. Later, such programmable logic devices incorporating erasable programmable read-only memory (EPROM) for configuration became available, allowing the devices to be reconfigured.
Still later, programmable logic devices incorporating static random access memory (SRAM) elements for configuration became available. These devices, which also can be reconfigured, store their configuration in a nonvolatile memory such as an EPROM, from which the configuration is loaded into the SRAM elements when the device is powered up. These devices generally provide the user with the ability to configure the devices for look-up table-type logic operations. At some point, such devices began to be provided with embedded blocks of random access memory that could be configured by the user to act as random access memory, read-only memory, or logic (such as P-TERM logic).
In all of the foregoing programmable logic devices, both the logic functions of particular logic elements in the device, and the interconnect for routing of signals between the logic elements, were programmable. More recently, mask-programmable logic devices have been provided. With mask-programmable logic devices, instead of selling all users the same device, the manufacturer manufactures a partial device with a standardized arrangement of logic elements, and which lacks any routing or interconnect resources.
The user provides the manufacturer of the mask-programmable logic device with the specifications of a desired device, which may be the configuration file for programming a comparable programmable logic device. The manufacturer uses that information to add additional metallization layers to the partial device described above. Those additional layers program the logic elements by making certain connections within those elements, and also add interconnect routing between the logic elements. Mask-programmable logic devices can also be provided with embedded random access memory blocks, as described above in connection with conventional programmable logic devices. In such mask-programmable logic devices, if the embedded memory is configured as read-only memory or P-TERM logic, that configuration also is accomplished using the additional metallization layers.
Because all but the earliest types of conventional programmable logic devices are reconfigurable as described above, testing of those devices, and particularly of embedded random access memory blocks thereon, is readily accomplished. In particular, after the device is manufactured, and before it is sold to a user, the device can be configured with a test configuration that tests the components of the device in any desired manner. The test configuration can be erased before the device is sold to a user. It is also possible for the user to load its own test configuration, which can then be erased prior to loading of the desired user application configuration.
On the other hand, mask-programmable logic devices cannot be reconfigured. Any test circuitry provided on the device is permanently present, and accordingly providing such circuitry either increases the die size of the device for a given level of functionality, or reduces the functionality for a given die size. It would therefore be desirable to provide a mask-programmable logic device, of the type having embedded random access memory blocks, with testing circuitry, the area (and hence the cost) of which has been minimized, as well as a method for testing such a device.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a mask-programmable logic device, of the type having embedded random access memory blocks, with testing circuitry, the area (and hence the cost) of which has been minimized, as well as a method for testing such a device.
This and other objects of the invention are accomplished in accordance with the principles of the invention by providing a mask-programmable logic device including an array of mask-programmable logic areas and a plurality of embedded memory blocks. Each of the embedded memory blocks is associated with one of the mask-programmable logic areas. Each of the embedded memory blocks has a set of read/write control registers, write data registers and data output registers associated therewith. The mask-programmable logic device also includes memory testing circuitry having first switching elements for chaining together at least some of the read/write control registers and the write data registers, and second switching elements for chaining together at least some of the data output registers. A test scan clock clocks data through the chains of read/write control registers and write data registers, and the chains of output registers.
By comparing data clocked in through one chain of registers on the input side of the embedded memory block or blocks with data clocked out another chain of registers on the output side of the embedded memory block or blocks, one can determine whether or not the output data are those which is expected based on the input data, which is an indication of whether or not the embedded memory block is functioning correctly.
The embedded memory blocks can be configured for testing before the testing begins, so that regardless of the configuration for which each has been programmed, each will emulate a common configuration during testing. Preferably, each embedded memory block acts as a 128×16 memory array. Where an embedded memory block has been configured as a read-only device—i.e., as a read-only memory or as a P-TERM logic unit—the values in the cells of the embedded memory block will nevertheless be output as though from the common configuration.
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Altera Corporation
Elms Richard
Fish & Neave
Ingerman Jeffrey H.
Le Toan
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