Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
1999-08-18
2001-06-26
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S220000, C365S221000
Reexamination Certificate
active
06252811
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the testing of semiconductor memories, and more specifically to a method and apparatus for increasing the speed of testing memory devices.
BACKGROUND OF THE INVENTION
During the manufacture of semiconductor memories, such as synchronous dynamic random access memories (“SDRAMs”), it is necessary to test each memory device to ensure that it is operating properly. One test performed on memory devices is the ability to accurately store data, sometimes known as functional testing. Typically this is implemented by writing a single data bit having a specific logic level, such as a logic one, into a single memory cell, and then reading the logic level of the data bit stored in that memory cell. If the logic level read is the same as the logic level that was written into that memory cell, then the memory cell has accurately stored the data bit, and the memory cell passes the test. If, however, the logic level of the data bit read from that memory cell is different than the logic level of data bit that was written into it, then the memory cell has not accurately stored the data bit, and the memory cell fails the test. These steps are then repeated until every memory cell in the memory device has been tested.
Functional testing typically requires three operations. First, a tester writes a data bit into the memory device under test. Second, the tester reads the data bit that was stored in the memory device. Third, the tester compares the logic level of the data bit read from the memory device with the logic level of the data bit that was written into the memory device. In order to compare the logic levels of the two data bits (one written, one read), the tester must generate or store the data bits that were written to the memory device. This allows the data bits that were written to be available to the tester when it compares the data bits read against the data bits that were written. The data bits written are typically algorithmically generated or stored in a data source device that is part of the tester, i.e., a data source device other than the memory device under test. Thus, a data source device is required for functional testing.
Every time the data bit read is compared to the data bit written, the tester must fetch from the data source device the data bits that were written to the memory device under test. This fetching requires a relatively large amount of time and increases the length of time it takes to test a memory device. Several factors limit the speed at which read cycles can be performed on a tester. The ability of the data source to supply the required compare data for the read (or write) cycle takes time. For redundancy purposes, failures that occur during a read cycle must be stored in a Catch RAM (“CRAM”) in the tester in order to facilitate redundancy analysis at a later time. The ability to write to the CRAM takes time, thereby limiting the speed of the read cycle. The speed at which the tester strobe (the strobe controls when the comparison of read data will take place and for what duration) can be repeated is limited by the tester circuitry. Thus, the frequency of the strobe limits the speed of the read cycle.
The three examples given above show how the read cycle time can be limited on a tester. This is significant because it is often possible to clock the device under test (DUT) at a much faster speed than the data source, CRAM, and read strobe can operate. Basically this means that the tester can exercise the part at a much greater speed than the tester's ability to verify correct functionality (typically done during a read cycle for RAMS). This is in fact the case for many memory tester vendors and the machines they produce for the purpose of functionally testing memory devices.
One example of a typical tester is a window strobe tester. A window strobe tester is active for a duration of time, the duration being known as a “window.” During this window, the tester determines if a single data bit read from the memory device under test has a specific logic level corresponding to the logic level of the stored data bit. The window is timed such that the data bit read from the memory device will be available during the entire period of the window. The tester checks for the specific logic level for the entire duration of the window. If that logic level is present during the entire window, it is assumed that the memory cell that stored that data bit has functioned correctly. Similarly, if the specific logic level is not present at any time during the window, it is assumed that the memory cell that stored that data bit has not functioned correctly.
One problem that exists with conventional memory testers is the result of a maximum operating speed of the tester. Each tester is designed to operate up to a particular operating speed. This speed typically does not change over the life of the tester. However, the operating speed of memory devices does change over time, and often increases greatly during the useful life of a tester. For example, a tester may have an operating speed of 16 MHz. During the first year of its use, the memory devices it tests may also have an operating speed of 16 MHz. However, the next year, the memory devices may have increased their operating speed to 64 MHz due to rapid advancements in technology. This results in a tester that can only test at one quarter (16 MHz/64 MHz={fraction (1/4+L )}) of the operating speed that technology allows. Thus, as technology allows for faster memory devices, the tester is not capable of testing the memory device at the full operating speed of the memory device.
It is desirable to have a tester that can test the memory devices at the maximum operating speed of the memory device. Testing memory devices at less than the maximum operating speed of the memory device may fail to find memory devices that will function satisfactorily at slower operating speeds but will fail to operate at the maximum operating speed. Also, testing memory devices at higher speeds allows more memory devices to be tested in a given amount of time. One way to test memory devices having ever increasing maximum operating speeds is to replace the tester with a new, faster tester each time the technology increases the operating speed of memory devices. This approach, however, can be quite expensive.
Thus, there is a need to allow memory testers to continue to be able to test memory devices at the maximum operating speeds of the memory devices as the maximum operating speeds increase beyond the operating speeds of the testers.
SUMMARY OF THE INVENTION
The present invention provides apparatus and methods for testing a memory device. A test circuit causes at least two data bits having a first logic level to be stored in respective memory cells of a memory device under test, and subsequently serially reads at least two data bits from the memory cells. The test circuit sequentially examines the logic level of the data bits read over a period of time that is part of the period that the data bits are available from the memory device. If the logic level changes during this period or is other than the first logic level, the memory cells from which the data bits are read are considered to be defective.
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Dorsey & Whitney LLP
Elms Richard
Micro)n Technology, Inc.
Nguyen Vanthu
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