Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2001-05-05
2004-01-20
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000, C365S185250
Reexamination Certificate
active
06681350
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a method and apparatus for testing logic circuits in general, and in particular to a method and apparatus for testing memory devices. Still more particularly, the present invention relates to a method and apparatus for testing memory cells for data retention faults.
2. Description of the Prior Art
Generally speaking, there are two types of faults that can occur in a cell array of a memory device, namely, parametric faults and functional faults. Functional faults can further be classified as coupling faults or single faults. Coupling faults are faults whereby a cell influences the behavior of another cell. Examples of coupling faults include inversion coupling faults, idempotent coupling faults, state coupling faults, linked coupling faults, etc. An inversion coupling fault involves two cells, one of which has its state inverted by a transition in the other cell. An idempotent fault also involves two cells, one of which is forced to a particular logic level by a transition write operation to the first cell. A state coupling fault is similar to inversion and idempotent coupling faults but differs in that the change in a cell results from some connection between two bitlines and not from a write transition. A linked coupling fault is when two or more coupling faults affect the same cell.
Single faults are faults that involve only a single cell. Single faults include stuck-at faults, stuck-open faults, transition faults, data retention faults, etc. A stuck-at fault occurs when the logic value of a cell is constant at a certain value, either zero or one.
A stuck-open fault is the inability of a cell to be accessed. A transition fault is the inability of a cell to undergo a zero to one transition or a one to zero transition. A data retention fault is the inability of a cell to maintain its logic level after some period of time.
Many static random access memory cells utilize a well-known six-transistor configuration, which includes a pull-up transistor on each side of the memory cell.
The advantage of a six-transistor configuration cell includes a higher operational stability and a higher alpha-particle immunity. One key disadvantage of a six-transistor configuration cell is, however, that certain open circuit failures in the pull-up or pull-down circuitry can appear as intermittent or soft failures. Because such faults do not result in a hard failure, testing and failure analysis have proven to be particularly difficult. Often times, extreme temperature cycling and sophisticated timing functions are employed during the manufacturing process, but still, not all defects can be detected.
By modelling such type of defects as data retention faults, the present invention provides an improved method and apparatus for detecting open circuit failures in the pull-up or pull-down circuitry of a six-transistor configuration cell.
BRIEF SUMMARY OF THE INVENTION
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a first logical value is stored in a first cell, and a second logical value is stored in a second cell of a memory device. The second cell shares a identical column with the first cell. The bitlines associated with the first and second cells are prevented from being precharged before the second cell can be read. After the second cell has been read repeatedly, the first cell is read, and the bitlines associated with the first and second cells are precharged. At this point, a data retention fault is determined to have occurred if the first cell does not contain the first logical value.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
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patent: 5361232 (1994-11-01), Petschauer et al.
patent: 5428574 (1995-06-01), Kuo et al.
patent: 5491665 (1996-02-01), Sachdev
patent: 5733032 (1998-03-01), Bolta et al.
patent: 5936902 (1999-08-01), Hsu et al.
patent: 6378102 (2002-04-01), Watanabe et al.
Adams R. Dean
Deo Aneesha P.
Zarrineh Kamran
Cadence Design Systems Inc.
Orrick Herrington & Sutcliffe LLP
Tu Christine T.
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