Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-11-06
2007-11-06
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S031000, C714S036000, C714S042000, C714S718000, C714S733000
Reexamination Certificate
active
10874300
ABSTRACT:
A method of testing a plurality of embedded memories within an integrated circuit. Each of the embedded memories include particular read and write protocols. The method includes providing a memory built in self test sequencer module and providing satellite engine module coupled to the memory built in self test sequencer module, to the plurality of embedded memories and applying read and write protocols to the plurality of embedded memories based upon the particular read and write protocols of each of the embedded memories. The satellite engine module includes an instruction buffer and a sequence generation engine.
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Daniel Ip Tse Wei
Zarrineh Kamran
Beausoliel Robert
Dorsey & Whitney LLP
Ehne Charles
Sun Microsystems Inc.
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