Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-09-28
2010-06-01
Puente, Emerson C (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C712S227000, C708S530000
Reexamination Certificate
active
07730356
ABSTRACT:
A method and apparatus for testing mathematical programs where code coverage is exceedingly difficult to hit with random data test vectors (probability <2−64) is provided. To enable testing of the mathematical program, instructions in the mathematical program are trapped. Errors are injected through the use of any status/control flag where an error can be created and be rectified later by a reversible operation so that the result of the mathematical operation is not modified by the injected error.
REFERENCES:
patent: 2003/0172321 (2003-09-01), Wolin et al.
patent: 2004/0044717 (2004-03-01), Makineni et al.
patent: 2005/0071818 (2005-03-01), Reissman et al.
patent: 2007/0174679 (2007-07-01), Chelstrom et al.
patent: 2009/0006517 (2009-01-01), Gopal et al.
patent: 2009/0089617 (2009-04-01), Gopal et al.
Cutter Daniel
Feghali Wajdi K.
Gopal Vinodh
Laurent Pierre
Milne Andrew
Fleming Caroline M.
Intel Corporation
Puente Emerson C
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