Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-03-29
2002-10-22
Ray, Gopal C. (Department: 2181)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C710S260000, C710S052000
Reexamination Certificate
active
06470463
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method and apparatus for testing the integrity of data transfer of a hardware used in a computer, and more particularly to a method and apparatus for parallel testing the integrity of data transfer of a hardware.
The current software process of testing a hardware, such as testing a modem, a serial or parallel port, or a hardware or software driver, is first to write testing data into the hardware, wait for the response of the hardware, then process the response for comparison and analysis. In other words, the testing method of prior arts first transfers testing data to the hardware from a computer. The hardware processes the data with an application program and generates a result. Then the hardware transfers the result to the computer for recording and display. The process is shown in FIG.
1
. After starting the test (step
10
), data are transferred to the hardware and processed with an application program (step
11
). Then the computer waits for the response data (step
12
) and displays the response data (step
13
). In the next step, the user can input instructions for further processing (step
14
), then the computer will execute the instruction (step
15
). Lastly, the computer checks if the test is finished (step
16
). If not, it proceeds the test; if yes, the test is finished or another test is proceeded (step
17
).
As described above, the test procedure of prior arts is a serial operation, i.e., the procedure in each step is executed one by one that a next step goes only after a prior step finishes. Therefore, it is a major disadvantage of prior arts that the serial procedure takes a longer time. For example, supposing a modem transferring data at a speed of 1 minisecond per character from a computer to an application program. The application program processes a text string at a speed of 3 miniseconds (ms) per word. Then, for a string “This is a test.” of 15 characters and 4 words, the transferring time is 15 miniseconds, added with the word processing time 12 miniseconds (4 ms *3=12 ms), the toted processing time will be 27 miniseconds. (The speed of inner process for executing programing and access of data is relatively fast in nanoseconds and can be neglected.)
Furthermore, since the string processing has to be started after receiving the whole string, there should be a buffer space for at least the 15 characters. And, since it involves a serial processing, the user cannot recognize the status of processing before the program finishes its operation. If any error or failure occurs, it will waste the time and cannot be earlier noticed. When testing a modem, since the working speed of a modem varies in a wide range, for example from 110 to 11520 baud, the response time differs widely. Especially when the modem works under different speeds of CPU or display cards, the time sequence is easy to be confused. Besides that, since the data transferring has a certain possibility rate of error which will cause variance of length of the received data, the conventional data receiving, in a manner of “receiving, processing, further receiving, further processing, . . . till finishing” requires a larger buffer space for the sequential processing and causes waste of buffer space.
SUMMARY OF THE INVENTION
The primary objective of the present invention is therefore to provide a testing module for speedy hardware testing which can expedite the data flow and requires less buffer space.
The key element of the invention is to replace the traditional serial procedure with a parallel procedure for hardware testing. In prior arts, the application program starts processing only after the whole data are received. But the processing of data is actually in a manner of character by character, instead of the whole data at once. In other words, the data processing can be started with partial data. Therefore, in the present invention, during receiving testing data, the application program starts getting characters from buffer and processing the data. In this manner, the data receiving and the data processing are proceeded at the same time. Therefore, the testing time of the whole data is decreased.
The present invention utilizes a method of direct access and hardware interruption. A ring buffer is first allocated, then the data are accessed by referring to a “PUT” tag and a “TAKE” tag. An interruption service is also provided, so, during data processing of the application program, the data receiving process is also continuing.
For the application program, since the testing data need not be fully read into the buffer, the buffer memory required for the present invention is less than that of prior arts. And, since the ring buffer and the PUT and TAKE tags, the status of the ring buffer can be detected by the application program with a certain time interval. The user thus can monitor the status at anytime and avoid wasting time if a failure of the testing occurs.
The objectives and advantages oft he present invention will become apparent from a detailed description provided below, with reference to the accompanying drawings.
REFERENCES:
patent: 3828325 (1974-08-01), Stafford et al.
patent: 5666559 (1997-09-01), Wisor et al.
patent: 6016521 (2000-01-01), Matsubara
Chen Hsuan-Tung
Dong Yan
Lin Kuang-Shin
Inventec C'orporation
Liauh W. Wayne
Ray Gopal C.
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