Method and apparatus for testing integrated circuits

Data processing: measuring – calibrating – or testing – Testing system – Of circuit

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C702S118000, C702S186000, C714S724000, C714S739000, C717S101000, C717S125000

Reexamination Certificate

active

07437261

ABSTRACT:
A distributed operating system for a semiconductor test system, such as automated test equipment (ATE), is described. The operating system includes a host operating system for enabling control of one or more site controllers by a system controller. One or more local operating systems, each associated with a site controller, enable control of one or more test modules by an associated site controller. Each test module performs testing on a corresponding device-under-test at a test site.

REFERENCES:
patent: 5892949 (1999-04-01), Noble
patent: 6028439 (2000-02-01), Arkin et al.
patent: 6405364 (2002-06-01), Bowman-Amuah
patent: 6427223 (2002-07-01), Kim et al.
patent: 6601018 (2003-07-01), Logan
patent: 6782336 (2004-08-01), Shah
patent: 2002/0073375 (2002-06-01), Hollander
patent: 2002/0183955 (2002-12-01), Adler
patent: 2003/0167277 (2003-09-01), Hejlsberg et al.
patent: 0 388 107 (1990-09-01), None
patent: 63-298177 (1988-12-01), None
patent: 63-298178 (1988-12-01), None
patent: 63-315971 (1988-12-01), None
patent: 04-204271 (1992-07-01), None
patent: 2000-162278 (2000-06-01), None
patent: 2000-163456 (2000-06-01), None
patent: WO-99/14609 (1999-03-01), None
International Search Report mailed on Jun. 29, 2004, for PCT application No. PCT/JP2004/001648 filed on Feb. 16, 2004, 4 pages.
Written Opinion mailed on Jun. 29, 2004, for PCT application No. PCT/JP2004/001648 filed on Feb. 16, 2004, 7 pages.
Japanese Office Action mailed on Apr. 11, 2006 for JP Patent Application No. 2006-502669 filed on Aug. 26, 2004, four pages (partial English translation).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for testing integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for testing integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for testing integrated circuits will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4018287

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.