Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2011-07-12
2011-07-12
Tabone, Jr., John J (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S719000
Reexamination Certificate
active
07979757
ABSTRACT:
A plurality of stacked memory device die and a logic circuit are connected to each other through a plurality of conductors. The stacked memory device die are arranged in a plurality of vaults. The logic circuit die serves as a memory interface device to a memory access device, such as a processor. The logic circuit die includes a plurality of link interfaces and downstream targets for transmitting received data to the vaults. The logic circuit die includes a packet builder and broadcaster configured to receive command, address and data signals over separate interfaces from a conventional tester, format the signals into a packet and broadcast the signals to a plurality of vaults.
REFERENCES:
patent: 5960008 (1999-09-01), Osawa et al.
patent: 6052329 (2000-04-01), Nishino et al.
patent: 6122688 (2000-09-01), Barth et al.
patent: 6363017 (2002-03-01), Polney
patent: 6401213 (2002-06-01), Jeddeloh
patent: 6519194 (2003-02-01), Tsujino et al.
patent: 6574626 (2003-06-01), Regelman et al.
patent: 6882304 (2005-04-01), Winter et al.
patent: 6907555 (2005-06-01), Nomura et al.
patent: 7058865 (2006-06-01), Mori et al.
patent: 7149134 (2006-12-01), Streif et al.
patent: 7168005 (2007-01-01), Adams et al.
patent: 7184916 (2007-02-01), Resnick et al.
patent: 7389375 (2008-06-01), Gower et al.
patent: 7567476 (2009-07-01), Ishikawa
patent: 7710144 (2010-05-01), Dreps et al.
patent: 2002/0004893 (2002-01-01), Chang
patent: 2002/0097613 (2002-07-01), Raynham
patent: 2002/0130687 (2002-09-01), Duesman
patent: 2002/0138688 (2002-09-01), Hsu et al.
patent: 2004/0073767 (2004-04-01), Johnson et al.
patent: 2004/0246026 (2004-12-01), Wang et al.
patent: 2005/0091471 (2005-04-01), Conner et al.
patent: 2005/0157560 (2005-07-01), Hosono et al.
patent: 2006/0126369 (2006-06-01), Raghuram
patent: 2006/0245291 (2006-11-01), Sakaitani
patent: 2006/0273455 (2006-12-01), Williams et al.
patent: 2007/0271424 (2007-11-01), Lee et al.
patent: 2008/0147897 (2008-06-01), Talbot
patent: 2009/0006775 (2009-01-01), Bartley et al.
patent: 2009/0016130 (2009-01-01), Menke et al.
patent: 2009/0196093 (2009-08-01), Happ et al.
patent: 2009/0300314 (2009-12-01), LaBerge et al.
patent: 2010/0005217 (2010-01-01), Jeddeloh
patent: 2010/0005376 (2010-01-01), LaBerge et al.
patent: 2010/0014364 (2010-01-01), LaBerge et al.
patent: 2010/0042889 (2010-02-01), Hargan
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Nguyen Steve
Tabone, Jr. John J
LandOfFree
Method and apparatus for testing high capacity/high... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for testing high capacity/high..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for testing high capacity/high... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2735093