Excavating
Patent
1989-12-29
1992-01-28
Beausoliel, Robert W.
Excavating
371 27, 364578, G06F 1100
Patent
active
050848763
DESCRIPTION:
BRIEF SUMMARY
The present invention relates to the testing of digital electronic assemblies.
Such assemblies exist at a large variety of complexities, from circuits consisting of discrete resistors and transistors, through circuit boards carrying a large number of VLSI integrated circuits, up to complete computer systems. It is frequently desirable or necessary to be able to test such assemblies.
At the lowest levels, testing individual components such as resistors and transistors often requires checking of parameter values; in this case, the components themselves are not being treated as digital devices. At the highest levels, testing is performed by the assemblies themselves running self-test programs. In between these two extremes, testing involves applying specially selected combinations of inputs to the assembly and monitoring the outputs. It is with this intermediate level that the present invention is primarily concerned.
The testing of such assemblies will often be at a sequence of different levels; if an assembly is found to be faulty, it may be broken down into subassemblies which are then tested individually. This breaking down may be achieved by physical disassembly or by the use of probes (e.g. bed-of-nails testers) reaching individual subassemblies in the complete assembly. In the latter case, the subassemblies are in principle being tested individually, although their responses will be complicated by the responses of those other subassemblies to which they are connected.
The present invention is particularly concerned with testing of assemblies which are treated as units--i.e. testing which involves only applying inputs to and monitoring outputs from the entire assembly without direct access to internal points or components of the assembly.
A further problem involved with testing is that of intermittent faults. These are notoriously hard to identify. The present invention is not concerned with such faults.
Given an assembly which requires testing, a test program--a combination of test inputs, or a sequence of such combinations--must be designed for it. With sufficiently simple assemblies, there is no problem in designing a test sequence; the testing can be exhaustive. A 2-input AND gate, for example, can be tested by applying all four possible combinations of inputs to it and monitoring the output (or both outputs, if it also has a complementary output). For more complicated assemblies, however, exhaustive testing is not possible, because the number of possible combinations of input bits rises exponentially with the number of inputs and because the number of possible internal states of the assembly also has to be taken into account if it goes beyond pure combinatorial logic to include any form of flip-flops or other storage.
It is possible to choose a random or pseudorandom sequence of test programs for use with such an assembly, on the assumption that a reasonably long such sequence will almost certainly detect any faults. Alternatively, it is possible to decide beforehand what faults are likely, and to attempt to design a test program which will detect such faults. This latter approach has hitherto involved treating the problem of designing the test programs as an intellectual puzzle.
The object of the present invention is to provide an automatic method and apparatus for generating, or assisting in the generation of, test programs for digital electronic assemblies for detecting predetermined faults.
A method and apparatus is provided for storing formal hierarchical descriptions to define an assembly without and an assembly with a fault. A representation is also stored of at least a part of the assembly derived from its formal description for the assembly without the fault and for the assembly with the fault. The stored representation is hierarchically expanded and simplified and discrimination conditions are extracted from the stored representation.
In accordance with this invention, the apparatus comprises means for storing the formal hierarchical descriptions sufficient to define the assembly without
REFERENCES:
patent: 4228537 (1980-10-01), Henckels
patent: 4868825 (1989-09-01), Koeppe
patent: 4961156 (1990-10-01), Takasaki
R. Lbath, "A Test Pattern Generation Environment for Complex Digital Circuits", ECE Session A, 4/1986, pp. 66-72.
S. Funatsu, "An Automatic Test-Generation System for Large Digital Circuits", 10/1985, pp. 54-60.
R. Hickling, "Automating Test Generation Closes the Design Loop", 11/1981, pp. 129-133.
M. Genesereth, "Diagnosis Using Hierarchical Design Models", 1985, pp. 278-283.
Gupta Ajay
Welham Robert K.
Beausoliel Robert W.
Hewlett--Packard Company
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