Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1997-09-19
1999-05-04
Quach, T. N.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438655, 438657, 438660, 438663, H01L 21283, H01L 21336
Patent
active
058997350
ABSTRACT:
A method for making low-resistance contacts between polysilicon and metal silicide on semiconductor integrated circuits is described. The method is particularly useful for making low contact resistance (R.sub.c) between the tungsten polycide word lines and the access (pass) transistors (FETs) on DRAMs. A first polysilicon/first silicide (polycide) layer is patterned to form a first polycide conducting layer for the FET gate electrodes. A dielectric layer is deposited over the patterned first polycide layer, and contact openings are anisotropically plasma etched in the dielectric layer to the surface of the first silicide layer. A second doped polysilicon layer is deposited on the substrate and over and in the contact openings contacting the first silicide layer. Prior to depositing a second silicide layer, a high-temperature rapid thermal process (RTP) or annealing is carried out to alter the second polysilicon/first silicide interface to reduce the contact resistance (about 10 ohms). This RTP eliminates the need for overetching the first silicide in the contact holes, as commonly practiced in the prior art. A second silicide layer is deposited and the second silicide/polysilicon (second polycide) is patterned to form the next level of interconnections, such as the word lines for the array of DRAM cells.
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Ackerman Stephen B.
Quach T. N.
Saile George O.
Vanguard International Semiconductor Corporation
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