Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-03-03
2008-11-04
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S005110, C714S025000, C714S030000, C714S042000, C714S719000, C714S723000, C714S724000, C714S730000, C714S733000, C714S734000, C714S738000, C714S742000, C714S799000
Reexamination Certificate
active
07447956
ABSTRACT:
Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write steering logic and reads the test patterns in parallel to test the write steering logic. The BIST controller writes test patterns to the memory in parallel and reads the test patterns through the read steering logic to test the read steering logic. In both cases, a separate comparator dedicated to each bus lane verifies that the subunit data was properly shifted between the data bus lane and memory storage location subunit. The comparators are effectively disabled during normal operations to prevent logic gate switching.
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Krishnamurthy Anand
Mamileti Lakshmikant
Mumford Clint Wayne
Patel Sanjay B
Ciccozzi John L.
Pauley Nicholas
QUALCOMM Incorporated
Rouse Thomas R.
Trimmings John P
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