Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-08-07
2007-08-07
Tu, Christine T. (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S734000
Reexamination Certificate
active
11034236
ABSTRACT:
The invention provides a test apparatus for testing a circuit unit to be tested. In one embodiment, a circuit unit incorporating aspects of the invention includes a data memory bank (106) for storing test mode data which are fed via an address control terminal (201) and with which the circuit unit (101) to be tested can be tested, provision being made of at least one test mode bank (104a-104n) for providing at least one test mode data set (204a-204n) and at least one activation signal (205a-205n), at least one register bank (103a-103n) and a transfer device for transferring a test mode data set (204a-204n) from a register bank (103a-103n) to the data memory bank (106) in a manner dependent on the activation signal (205a-205n).
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Infineon - Technologies AG
Maginot Moore & Beck
Tu Christine T.
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