Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-07-19
2005-07-19
Beausoliel, Robert (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S037000
Reexamination Certificate
active
06920582
ABSTRACT:
A method and apparatus for testing by sampling vectors circuit modules designated as channel models or as control modules and containing scan chains. Use is made of a test register which provides at least one control sampling mode signal for control modules and furthermore provides at least one channel sampling mode signal for channel modules. Channel modules and control modules can occur as circuit modules multiply with identical scan chains, enabling efficient testing in a manner that saves memory space. A logic is designed for the read-out of sampling output signals after testing of the scan chains via a read-out terminal unit of a test device, thus providing a comparison with desired sampling output signals for channel modules or for control modules in a comparator unit.
REFERENCES:
patent: 5961653 (1999-10-01), Kalter et al.
patent: 6661266 (2003-12-01), Variyam et al.
patent: 6662313 (2003-12-01), Swanson et al.
patent: 6691252 (2004-02-01), Hughes et al.
Alt Juergen
Valentin Frederic
Beausoliel Robert
Bonura Timothy M.
Infineon - Technologies AG
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