Error detection/correction and fault detection/recovery – Pulse or data error handling – Skew detection correction
Reexamination Certificate
1999-03-30
2001-08-28
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Skew detection correction
Reexamination Certificate
active
06282676
ABSTRACT:
FIELD OF INVENTION
The present invention relates to a method and an apparatus for testing and debugging a first IC device, and in particular, to a method and an apparatus for testing an IC device by use of a second IC device which is identical to the first IC device and has been confirmed to be error-free.
BACKGROUND OF INVENTION
After being manufactured, an IC device must be tested functions thereof to assure quality thereof With respect to the testing of IC devices, a conventional approach utilizes a series of test patens to test functions of a tested IC device. By the series of test patens, the designer attempts to emulate all possible conditions under the actual operation environment in the test environment, but it is usually impossible. To date, the conventional approach in which one individual IC device is tested under a series of test patens is still employed in several prior arts, e.g., U.S. Pat. Nos. 4,928,278 and 5,432,797.
However, according to the practical experiences, one IC device, which pass the function test of the conventional approach, may still malfunction under actual operation environment. This cause is that the test patens and fault coverage of the conventional approach cannot accurately emulate whole possible conditions under actual environment. Moreover, for detecting the error point of the malfunctioning IC device, the designer must add other test patens to the series of test patens and then re-test the IC device. The procedure mentioned above is repeated until the error point of the IC device is detected. It is evident that the conventional approach consumes much time and cost, and that the test reliability of the IC device tested by the conventional approach is very low.
Accordingly, an objective of the invention is to provide a rapid and reliable method for testing and debugging an IC device. In particular, the invention provides a method for testing and debugging a first IC device by use of an error-free second IC device. The second IC device is identical to the first IC device, i.e., the first and second IC devices follow the same specification and have the same I/O layout. The method of the invention can detect an error point of one malfunctioning IC device accurately. Furthermore, the I/O history of the malfunctioning IC device ahead and behind of the error point thereof can be monitored. This can provide accurate test result and valuable reference for correction of the malfunctioning IC device.
The concept and spirit of this present invention are applicable to digital and analog types of IC devices.
SUMMARY OF INVENTION
An objective of the invention is to provide a method for testing and debugging a first IC device by use of an error-free second IC device. The second IC device is identical to the first IC device, i.e., the first and second IC devices follow the same specification and have the same I/O layout. The error-free second IC device means that the second IC device has been confirmed to operate normally under actual operation environment. The invention can shorten test time and enhance test reliability for the function test of the first IC device.
According to the invention, the method utilizes a test apparatus including a comparator circuit and communicating with a computer system via bus including a clock signal. A testing utility is executed in the computer system during the test. The comparator circuit compares output of the first IC device with output of the second IC device, and is operated by the clock signal to generate an error signal when a predetermined criterion is met. The concept and spirit of the invention are applicable to digital and analog types of IC devices.
According to the invention, an apparatus is provided for testing a first IC device by use of an error-free second IC device identical to the first IC device. The apparatus communicates with a computer system via a bus. The bus includes a clock signal outputted from the computer system in which a testing utility is executed during test. The apparatus comprises a comparator circuit, a first connection device, and a second connection device. The comparator circuit is operated by the clock signal, and communicates with the first IC device and the second IC device via first I/O lines and second I/O lines, respectively. The first connection device is provided for making connection of the first IC device to the computer system via the bus and to the comparator circuit via the first I/O lines, respectively. The second connection device is provided for making connection of the second IC device to the computer system via the bus and to the comparator circuit via the second I/O lines, respectively. The comparator circuit compares data on the first I/O lines and the second I/O lines for generating an error signal when a predetermined criterion is met. By comparing with the error-free second IC device, the first IC device can be detected error points thereof accurately, if it has, only under the test utility rather than a larger number of test patens. Consequently, with the test apparatus according to the invention, the test time of the first IC device can be shorten and the test reliability of the first IC device can be enhanced.
REFERENCES:
patent: 4928278 (1990-05-01), Otsuji et al.
patent: 5319224 (1994-06-01), Sakashita et al.
patent: 5432797 (1995-07-01), Takano
Brothers Coudert
Chung Phung M.
Winbond Electronics Corp.
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