Method and apparatus for testing and debugging a tightly coupled

Details Method and apparatus for testing and debugging a tightly coupled Method and apparatus for testing and debugging a tightly coupled

1992-10-02

1995-07-18

Nguyen, Hoa T.

Excavating

371 683, 371 151, G06F 1100, G06F 1540

Patent

active

054349974

ABSTRACT:
A method and apparatus for operating tightly coupled mirrored processors in a computer system. A plurality of CPU boards are coupled to a processor/memory bus, commonly called a host bus. Each CPU board includes a processor as well as various ports, timers, and interrupt controller logic local to the respective processor. The processors on one or more CPU boards are designated as master processors, with the processors on the remaining CPU boards being designated as mirroring or slave processors. A master processor has full access to the host bus and a second, multiplexed bus for read and write cycles, whereas the slave processors are prevented from writing to any bus. The slave processors compare write data and various control signals with that generated by its respective master processor for disparities. The system includes interrupt controller synchronization logic to synchronize interrupt requests as well as timer synchronization logic to synchronize the timers in each of the master and slave CPUs to guarantee that the master and slave CPUs operate in lockstep.

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