Synchronous/asynchronous clock net with autosense

Details Synchronous/asynchronous clock net with autosense Synchronous/asynchronous clock net with autosense

1993-12-28

1995-07-18

Kriess, Kevin A.

Boots, shoes, and leggings

395325, 395500, 395800, 395725, 395275, 395250, 364231, 3642329, 3642397, 3642474, 3642705, 364DIG1, G06F 1300, H04L 702

Patent

active

054349966

ABSTRACT:
A circuit within a bus bridge operating in a first clock domain and a second clock domain, wherein the circuit allows data, address or any other information to be reliably transferred between the first and second clock domains regardless whether or not an internal bus clock of the second clock domain is operating in a synchronous or asynchronous fashion, while the circuit still minimizes clock skew between the internal bus clocks of both clock domains as well as any corresponding external bus clocks.

REFERENCES:
patent: 4785469 (1988-11-01), Joshi et al.
patent: 4916717 (1990-04-01), Sackman, III et al.
patent: 5191657 (1993-03-01), Ludwig et al.
patent: 5339395 (1994-08-01), Pickett et al.
"The Metaflow Architecture", Val Popescu, Merle Schults, John Spracklen, Gary Gibson, Bruce Lightner and David Isaman, IEEE Micro, Jun. 1991 (pp. 10-13, 63-73).

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