Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2001-02-20
2004-08-10
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S042000, C714S718000, C711S100000, C711S118000, C365S203000
Reexamination Certificate
active
06775795
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method and an apparatus for testing an SDRAM memory used as a main memory in a personal computer (PC) and, in particular, is concerned with activation and carrying out predetermined and chip-internal test modes, which are defined in the SDRAM memory by the manufacturer, during normal use of the SDRAM memory as the main memory in a PC.
Various manufacturers integrate specific functions (test modes), which allow the SDRAM to be tested more efficiently in their modules. Until now, these test modes could be activated only by special test equipment, but could not be carried out in the typical SDRAM operational conditions in a computer.
Tests of SDRAMs that led to sporadic failures in the computer were particularly difficult. Sporadic failures such as these cannot be confirmed, or can be confirmed only rarely, on the test equipment.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method and an apparatus for testing an SDRAM memory used as the main memory in a personal computer which overcome the above-mentioned disadvantages of the prior art methods and devices of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for testing a SDRAM memory used as a main memory in a personal computer (PC) in which manufacturer-defined internal test modes are implemented. The method includes the steps of:
a) storing, in machine code, at least one command sequence suitable for activating and carrying out at least one of the internal test modes, in an additional memory being separate from the main memory;
b) activating the machine code in the PC and switching-off a cache memory of the PC;
c) changing a central processing unit (CPU) in the PC to an UNREAL mode resulting in data segmentation in the main memory being cancelled;
d) setting in the PC, predetermined settings of a PC chip set for an activation sequence of an internal test mode;
e) selecting a desired test mode of the internal test modes available in the SDRAM memory on a user-defined basis and making a read access to the additional memory for carrying out the command sequence for activation of the desired test mode;
f) activating the desired test mode by a specific sequence of commands and addresses being supplied from a memory controller to the SDRAM memory, the specific sequence of commands being controlled by the command sequence stored in the additional memory; and
g) recording test results.
The object of the invention is therefore to specify a method and an apparatus for testing an SDRAM memory used as the main memory in a PC, by activation of at least one test mode implemented in the SDRAM such that the test mode can also be activated and carried out during standard operation of the SDRAM in the computer. In this way, more efficient testing of the SDRAM in its normal application as the main memory in the PC is possible.
The method according to the invention allows all the test modes implemented in the SDRAM to be carried out in a standard PC using standard operating systems. This greatly increases the options for testing SDRAMs on standard PCs. Furthermore, the various test modes implemented in the SDRAM for the first time allow different module-internal parameters, such as voltages and timings, to be varied deliberately, while the SDRAM is operating in the PC, in order to analyze the actual cause of the fault in this normal SDRAM environment in a standard computer.
After carrying out the already activated test mode and recording the test results, the PC chip set settings carried out are cancelled. In addition, the data segmentation in the main memory is reproduced by changing the CPU to the REAL mode, the CACHE memory is switched on again and a jump is made back to the calling program, with the SDRAM memory remaining in the selected test mode, so that its effect is retained in the SDRAM memory. A parameter which has been changed by this effect in the SDRAM memory can then be used to initiate either the normal main memory mode or any desired test software implemented in the PC.
The method according to the invention thus not only allows improved analysis and improved testing of SDRAM modules in their normal environment in the PC, but also allows the configuration of SDRAM chips to be improved. By way of example, it is possible to test different timings with the aid of test modes in the system, in order to use the optimum setting for final configuration of the chip. Thus, by changing parameters within the module, the chip can be optimized to such an extent that optimum operation of the chip in a standard computer is ensured and these settings are then used for final chip design.
One application of the method according to the invention is also to systematically increase or reduce the failure rate of an SDRAM chip in the computer. The behavior of the chip provides information as to how the test programs in the test equipment must be modified in order that failures in the test equipment can also be coped with. The actual fault cause can be further localized and completely analyzed by further variation of internal parameters in the SDRAM module.
The method according to the invention thus provides a new and advantageous tool for analysis of SDRAM modules in their operational environment.
By way of example, one test mode that can be activated using the method according to the invention is a test mode which is referred to as SET-V-REF, which makes it possible to vary the internal reference voltage V
ref
in an SDRAM chip. The testing can be carried by using standard values of the reference voltage.
A further test mode which can be carried out using the method according to the invention for an SDRAM chip used in a PC is to vary an internal time period, in the SDRAM, between activation of the word line and activation of the associated sense amplifier.
In order to allow the test modes to be activated in the main memory of the PC, that is to say in the SDRAM, the additional memory, which is independent of the main memory, for program running is required in the PC.
An apparatus according to the invention and set up to carry out the method is characterized in that the additional memory is provided with coding logic on a plug-in board. The additional memory is programmed to carry out the steps a)-g) mentioned above. The plug-in board can, for example, be plugged into a plug-in slot for the ISA bus in the PC. Instead of this, the plug-in board may also, for example, be a PCI plug-in board. The sequence for activation of the test modes is thus carried out in machine code using this circuit configuration.
The command sequence stored on the plug-in board can be used deliberately to change the SDRAM, which is located in the module bank in the main memory, in the running PC to one of a number of test modes which can be selected. In this case, the machine code for activation of the test mode is modified by a high-level language program in accordance with user commands which are preset on a user interface, are copied to the additional memory, and are then called by the high-level language program using MS DOS. After activation of the selected test mode by the machine code, a defined jump is made back to the calling program once again.
In accordance with a concomitant feature of the invention, the plug-in circuit board is a 16-bit ISA board and, the additional memory is formed from two 8-bit SRAM modules with an overall data access width of 16 bits.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method and an apparatus for testing an SDRAM memory used as the main memory in a personal computer, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of th
Doll Andreas
Moser Manfred
Schramm Achim
De'cady Albert
Gandhi Dipakkumar
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
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