Method and apparatus for testing an integrated memory device

Details Method and apparatus for testing an integrated memory device Method and apparatus for testing an integrated memory device

1998-04-17

2000-07-04

Butler, Dennis M.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 8, 714 30, 714710, H02H 305

Patent

active

060853344

ABSTRACT:
A method of memory array testing that detects defects which are sensitive to environmental conditions. A repair signature is generated reflecting the repair state of the memory. A memory device is rejected if there is a change in the repair signature of the memory array over the operating range of the device. In one embodiment, an integrated circuit includes a memory array, spare memory elements for repairing defective locations of the memory array, a built-in self-test (BIST) circuit for detecting faults in the memory array, a built-in self-repair (BISR) circuit for causing the failed memory location of the memory array to be replaced with a spare memory element, and a signature generator where the signature is based on a compression of addresses corresponding to failed memory locations, wherein the signature is used to determine that a repair result of the memory array is invariant over different environmental conditions.

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Jeffrey Dreibelbis et al., "Processor-Based Built-In Self-Test for Embedded DRAM", Nov. 1998 IEEE Journal of Solid-State Circuits, vol. 33, No. 11, pp. 1731-1740.
"Built-In Self-Repair Circuit for High-Density ASMIC", Sawada, et al.; IEEE 1989 Custom Integrated Circuits Conference; pp. 26.1.1-26.1.4.

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