Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1995-08-25
2000-04-18
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
365201, G01R 3128
Patent
active
060528060
ABSTRACT:
An integrated circuit device includes operational circuitry, for example, in the form of a memory for carrying out operations of the integrated circuit device. Additionally, at least one peripheral circuit is connected to the operational circuitry for carrying out at least one function in respect of the operational circuitry. Input means are provided to permit the input of command data in a normal mode of operation and to permit the input of test data in a test mode of operation. Control circuitry has an input to receive command data from the input means. The control circuitry is arranged to generate, in response to the command data, control signals to control at least one of the peripheral circuits in the normal mode of operation. A control bus is connected between the control circuitry and the peripheral circuits and is arranged to carry control signals from the control circuitry to at least one peripheral circuit. Test circuitry is also provided which has an input arranged to receive test data from the input means. The test circuitry also has an output connected to the control bus and is arranged such that in the test mode of operation, the test data is supplied to at least one peripheral circuit from the test circuitry via the control bus.
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Beausoliel, Jr. Robert W.
Carlson David V.
Galanthay Theodore E.
Iqbal Nadeem
STMicroelectronics Limited
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