Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-05-27
2002-07-23
Beausoleil, Robert (Department: 2782)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C326S030000, C326S082000
Reexamination Certificate
active
06425097
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to input/output (I/O) buffers used to drive signals upon, and receive signal from, transmission lines, and more particularly to the testing of impedance-controlled I/O buffers.
2. Description of the Relevant Art
Digital electronic devices typically communicate via electrical signals (e.g., voltage and/or current) driven upon electrical conductors (e.g., metal wires). As the operating frequencies (i.e., “speeds”) of digital electronic devices increase, electrical conductors used to route signals between components (i.e., signal lines) begin to behave like transmission lines. Transmission lines have characteristic impedances. If the input impedance of a receiving device connected to a transmission line does not match the characteristic impedance of the transmission line, a portion of an incoming signal is reflected back toward a sending device. Such reflections cause the received signal to be distorted. If the distortion is great enough, the receiving device may erroneously interpret the logical value of the incoming signal.
Binary digital signals typically have a low voltage level associated with a logic low (i.e., a logic “0”), a high voltage level associated with a logic high (i.e., a logic “1”), “rise times” associated with transitions from the low voltage level to the high voltage level, and “fall times” associated with transitions from the high voltage level to the low voltage level. A signal line behaves like a transmission line when the signal rise time (or signal fall time) is short with respect to the amount of time required for the signal to travel the length of the signal line (i.e., the propagation delay time of the signal line). As a general rule, a signal line begins to behave like a transmission line when the propagation delay time of the signal line is greater than about one-quarter of the signal rise time (or signal fall time).
Resistive “termination” techniques are often applied to transmission lines, and signal lines long enough to behave like transmission lines, in order to reduce reflections and the resultant signal distortion. One or more electrically resistive elements may be inserted between each sending device and the signal line (i.e., transmission line) in order to cause the effective output impedances of the sending devices to more closely match the characteristic impedance of the transmission line. Similarly, one or more electrically resistive elements may be inserted between each receiving device and the transmission line in order to cause the effective input impedances of the receiving devices to more closely match the characteristic impedance of the transmission line.
Impedance-controlled buffers are often used to drive “unterminated” transmission lines. In order to reduce signal reflections and distortion, the output impedance of an impedance-controlled I/O buffer connected to a transmission line is adjusted such that the output impedance is substantially equal to the characteristic impedance of the transmission line. Several factors may affect this impedance matching, including: (i) device variations due to variations in the fabrication process, (ii) supply voltage variations, and (iii) operating temperature variations. As a result, the output impedances of impedance-controlled I/O buffers are generally made variable and controllable by a one or more logic signals.
FIG. 1
is a block diagram of an exemplary impedance-controlled I/O buffer
10
. I/O buffer
10
includes a pre-driver section
12
coupled to a driver section
14
. Pre-driver section
12
receives an input data signal “DATA_IN” at a data input terminal labeled “DATA_IN”. Pre-driver section
12
also receives binary p-channel transistor enable signals “EP
1
-EP
5
” and n-channel transistor enable signals “EN
1
-EN
5
” (e.g., from a control unit). Pre-driver section
12
may include logic elements which produce p-channel transistor control signals “P
1
-P
5
” from enable signals EP
1
-EP
5
and input data signal DATA_IN, and n-channel transistor control signals “N
1
-N
5
” from enable signals EN
1
-EN
5
and input data signal DATA_IN. Driver section
14
receives p-channel transistor control signals P
1
-P
5
and n-channel transistor control signals N
1
-N
5
and produces an output data signal “DATA_OUT” at an data output terminal labeled “DATA_OUT”.
FIG. 2
is a circuit diagram of an exemplary embodiment of driver section
14
. Driver section
14
includes five driver pairs
16
-
20
. Each driver pair includes a p-channel transistor and an n-channel transistor connected in series between a first power supply voltage V
DD
and a second power supply voltage V
SS
, where V
DD
>V
SS
. Within each driver pair, a source region of the p-channel transistor is connected to V
DD
, a drain region of the p-channel transistor is connected to a drain region of the corresponding n-channel transistor at an output node, and a source region of the n-channel transistor is connected to V
SS
. The output nodes of all five driver pairs are connected to the DATA_OUT terminal of I/O buffer
10
as shown in FIG.
2
.
Each driver pair of driver section
14
has an output electrical impedance which is largely resistive and inversely related to the current sourcing and sinking capability of the driver (i.e., the “drive strength” of the driver pair). The driver pairs may be configured such that the relative drive strengths double from one driver pair to the next. For example, a first driver pair
16
may have a base or reference drive strength, and a corresponding base or reference output impedance. A second driver pair
17
may have a drive strength twice the drive strength of driver pair
16
, and an output impedance half that of driver pair
16
. A third driver pair
18
may have a drive strength twice that of second driver pair
17
and 4 times the drive strength of first driver pair
16
, and an output impedance one-fourth that of driver pair
16
. A fourth driver pair
19
may have a drive strength twice that of third driver pair
18
and
8
times the drive strength of driver pair
16
, and an output impedance one-eighth that of driver pair
16
. A fifth driver pair
20
may have a drive strength twice that of fourth driver pair
19
and
16
times the drive strength of driver pair
16
, and an output impedance one-sixteenth that of driver pair
16
.
The transistors of driver section
14
need not be enabled in pairs, hence the separate enable signals EP
1
-EP
5
and EN
1
-EN
5
. When the DATA_IN signal is a logic high (i.e., a logic ‘1’), at least one p-channel transistor of driver section
14
is enabled by a corresponding enable signal EPx, where x is an integer between 1 and 5, and the output impedance “Z
OUT
” of I/O buffer
10
is a parallel combination of the impedances of all of the enabled p-channel transistors. Similarly, when the DATA_IN signal is a logic low (i.e., a logic ‘0’), at least one n-channel transistor of driver section
14
is enabled by a corresponding enable signal ENx, and the output impedance Z
OUT
of I/O buffer
10
is a parallel combination of all of the enabled n-channel transistors. Each transistor of driver section
14
has a different impedance inversely related to its current sourcing or sinking capability, thus the output impedance of I/O buffer
10
may be controlled by selectively asserting enable signals EP
1
-EP
5
and EN
1
-EN
5
.
The DATA_OUT terminal of I/O buffer
10
may be connected to one end of a transmission line, and enable signals EP
1
-EP
5
and EN
1
-EN
5
may be selectively enabled (e.g., by a control unit) such that the output impedance Z
OUT
of I/O buffer
10
is substantially equal to the characteristic impedance of the transmission line. As a result, errors resulting from signal reflections and distortion may be reduced. Additionally, the values of enable signals EP
1
-EP
5
and EN
1
-EN
5
may be adjusted during operation to compensate for changes in the output impedance Z
OUT
of I/O buffer
10
due to variations in power supply voltages and/or variations in temper
Elachkar Samir M.
Le Thomas
Beausoleil Robert
Conley Rose & Tayon PC
Kivlin B. Noäl
Sun Microsystems Inc.
Wilson Yolanda
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