Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-12-05
2004-11-16
Tang, Minh N. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06819129
ABSTRACT:
BACKGROUND
The present invention relates to test technology for semiconductor devices, and more particularly, to a method and apparatus for testing non-standard memory devices under actual operating conditions.
FIG. 1
illustrates a conventional process for fabricating and testing semiconductor integrated circuit (IC) devices and a printed circuit board onto which the IC devices are assembled. First, numerous semiconductor devices are fabricated in a semiconductor wafer
10
. The semiconductor devices are tested at the wafer-level, and faulty devices are selectively marked for disposal during a sorting process. Non-faulty devices are then separated from the wafer.
The individual semiconductor devices that pass the wafer-level test are then assembled into packages. The packaged devices
20
are tested at the package-level by using a burn-in test, which screens out early defects under extreme temperature and electrical conditions, and a functional test, which determines the electrical characteristics of the devices. Good devices that pass the package-level tests are assembled into printed circuit board-type products (such as memory module
30
shown in FIG.
1
). The board-type products are also tested after assembly.
A disadvantage of the conventional test process described above is that test conditions do not always correspond to actual operating conditions that the semiconductor devices encounter during actual use. Therefore, even if a packaged device passes the burn-in and the functional tests, there might exist some defects that cannot be detected until the device is assembled into the board-type product. This increases production costs due to the expense associated with repairing and retesting the product or, if repair is not possible, with scrapping the product.
For example, a large number of semiconductor memory devices are assembled into a board-type memory module such as a Single Inline Memory Module (SIMM) or a Dual Inline Memory Module (DIMM). Such memory modules are typically installed onto a system-level board such as the motherboard of a computer system. Even if the module contains only one memory device that does not operate properly after installation, the entire module must be disposed of because it is prohibitively expensive to remove and replace the improperly operating device which is soldered onto the module.
Another drawback of the conventional test process is that conventional test equipment is complicated, bulky and expensive. Manufacturers of semiconductor memory devices typically utilize testers such as the Hewlett Packard model HP83000 tester and the Advan tester to test the packaged devices. These testers generate test signal patterns that simulate memory bus signals (e.g., clock, row address strobe (RAS), column address strobe (CAS), data and address signals) which the memory device will receive from a central processing unit (CPU) or chipset when utilized in the system level board. The test signals are applied to the terminal leads of the memory device under test (DUT), and then the tester analyzes signals received back from the memory device to determine whether the electrical characteristics are acceptable. Although this type of tester is very flexible and therefore capable of a broad range of tests, it cannot provide an environment identical to that encountered during actual operation. Furthermore, to provide this test flexibility, the tester becomes more complicated, and thereby more difficult and more expensive to operate and program.
To provide a more realistic test environment, a board-type product such as a memory module can be tested on a system-level test substrate that provides test conditions that more nearly corresponds to an actual operating environment. For example, the board-type device can be mounted the motherboard of a computer system which is used as a test substrate to test the board-level device under actual operating conditions. In general, such a board-type product complies with relevant international standards such as Joint Electron Device Engineering Council (JEDEC), and the system-level test substrate such as a motherboard of a computer system has a socket for receiving the board-type product.
The test substrate used for the actual test is suitable for JEDEC standard memory modules, but not for non-standard memory modules, that is, custom-made memory modules. For example, when a 200-pin DIMM, which is a custom-made module for a high-performance server, is mounted on a test substrate for a JEDEC standard 168-pin DIMM used in most desktop computers, the memory devices do not operate properly because the operating environment provided by the test substrate is different from the actual operating environment for the 200-pin DIMM.
SUMMARY OF THE INVENTION
One aspect of the present invention is a system for testing a non-standard memory device under actual operating conditions. The system comprises an interface board having a first surface, a second surface, and a pin matching circuit. A socket on the first surface can couple the non-standard memory device to the pin matching circuit, and the second surface is constructed and arranged to couple the pin matching circuit to a standard pin configuration. The second surface of the interface board can be mounted directly on the test substrate. Alternatively, a second socket on the second surface of the interface board can be used to couple the pin matching circuit to the test substrate.
The pin matching circuit can comprise a first matching unit for allowing a one-to-one correspondence between signals of the standard pin configuration and non-standard pin configurations. The pin matching circuit can further comprise a second matching unit to selectively assign signals of the standard pin configuration to signals of the non-standard pin configuration.
Another aspect of the present invention is a method for testing a memory device having a non-standard pin configuration under actual operating conditions comprising. The method comprises coupling the memory device to an interface board that is constructed and arranged to adapt the non-standard pin configuration of the memory device to a standard pin configuration on a test substrate, and operating the test substrate.
A further aspect of the present invention is an interface board for an actual test of a non-standard memory device. The interface board comprises a circuit board including a first surface, a second surface, and a circuit layer. The interface board further comprises a first socket, which is formed on the first surface of the circuit board to receive the non-standard memory device for electrically connecting the memory devices and the circuit layer. The interface board still further comprises a second socket, which is formed on the second surface of the circuit board, to electrically connect the circuit layer and a standard test substrate. In particular, the interface board comprises a pin matching circuit, which is formed in the circuit layer, to match the standard pin configuration of the test substrate to the non-standard pin configuration of the non-standard memory device.
The pin matching circuit may include a first matching unit and a second matching unit. The first matching unit allows a one-to-one correspondence that uniquely assigns each standard input of control signals and address signals of the standard pin configuration to each non-standard output of control signals and address signals of the non-standard pin configuration. The second matching unit allows a sequential and interleaving link that selectively assigns each standard input of data input/output signals of the standard pin configuration to each non-standard output of data input/output signals of the non-standard pin configuration.
The interface board may further comprise a clock inverter circuit, which is formed in the circuit layer to selectively or simultaneously enable two clock signals of the non-standard pin configuration in response to one clock signal of the standard pin configuration.
Another aspect of the present invention is an actual testing s
Kim Chang-Nyun
Kim Sun-Ju
Park Hyun-Ho
Park Sang-Jun
Seo Jin-Seop
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
Tang Minh N.
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