Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2011-05-31
2011-05-31
Chung, Phung M (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S736000
Reexamination Certificate
active
07954020
ABSTRACT:
A system and method for testing a memory array are disclosed which may include establishing a stored data vector, including a plurality of data bits, within at least one circuit; applying one or more logical operations on the stored data vector to generate a succession of original data vectors at the at least one circuit; transmitting the succession of original data vectors through a memory array to provide a succession of exercised data vectors; comparing the succession of exercised data vectors to the succession of respective original data vectors; and determining whether the memory array passes or fails based on the comparing step.
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Office Action for co-pending U.S. Appl. No. 11/691,838 dated: Jun. 11, 2009.
Co-pending U.S. Appl. No. 11/691,838, filed Mar. 27, 2007.
Chung Phung M
Dernier Matthew B.
Gibson & Dernier LLP
Sony Computer Entertainment Inc.
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