Method and apparatus for testing a CAM addressed cache

Details Method and apparatus for testing a CAM addressed cache Method and apparatus for testing a CAM addressed cache

2005-06-21

2005-06-21

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S049130, C714S030000, C714S718000, C714S719000

Reexamination Certificate

active

06909651

ABSTRACT:
In one embodiment, an array of content addressable memory (CAM) cells include a first plurality of CAM cells and a second plurality of CAM cells. The second plurality of CAM cells has a width sufficient to address a height of the array. A first plurality of CAM drivers are coupled to the array to drive the first plurality of CAM cells. The first plurality of CAM drivers prevent the first plurality of CAM cells from participating in a match when the array is in a test mode.

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