Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1999-03-17
2001-08-14
Auve, Glenn A. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
Reexamination Certificate
active
06275887
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of bus architecure, and more particularly to the field of increasing bus utilization in an electronic system.
BACKGROUND OF THE INVENTION
It is often possible to increase the performance of an electronic system by increasing the utilization of a bus in the system. For example, it might be possible to increase the performance of a computer system having a Peripheral Component Interconnect (PCI) bus according to the PCI Local Bus Specification, Revision 2.1, published July 1995, by increasing the utilization of the PCI bus.
According to a well known approach, wait states are inserted into a pending PCI transaction when the device that is the target of the transaction is not ready to complete the transaction. Wait states continue to be inserted until either the target is ready to complete the transaction or a timer in the target expires. In either case, the bus is not available for other transactions during the pending transaction. If another bus master is ready to initiate another transaction during the pending transaction, then a potential increase in bus utilization will be lost. Also, in the case of termination due to an expiring timer, a potential increase in bus utilization will be lost if the target would have been ready to complete the transaction after the timer expires but before another bus master is ready to initiate a transaction.
Therefore, a novel approach to terminating a bus transaction if the target is not ready has been developed.
SUMMARY OF THE INVENTION
A bus target device is disclosed. The bus target device includes a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit is configured to detect whether the bus target device is the target of a first transaction initiated by a first bus master device. The second circuit is configured to determine whether the bus target device is ready to complete the first transaction. The third circuit is configured to determine whether a second bus master device is ready to initiate a second transaction. The fourth circuit is configured to terminate the first transaction if the bus target device is the target of the first transaction and is not ready to complete the first transaction and the second bus master device is ready to initiate the second transaction.
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Derr Michael N.
Riesenman Robert J.
Auve Glenn A.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
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