Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1999-02-18
2001-09-11
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S206000
Reexamination Certificate
active
06289430
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the data processing field, and more particularly, relates to a method and apparatus for target addressing and translation in a non-uniform memory environment with user defined target tags.
DESCRIPTION OF THE RELATED ART
Integration of a microprocessor core onto a chip, such as a communications adapter chip, brings with it a number of challenges. The number and types of addressable memory spaces/devices or Targets directly accessible by the processor can significantly increase.
Also the Targets may have different access characteristics, such as different speeds, organization, side effects, overlapping and/or non-contiguous address ranges and the like.
A need exists for an effective mechanism for target addressing and translation in a non-uniform memory environment.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an improved method and apparatus for target addressing and translation in a non-uniform memory environment with user defined target tags. Other important objects of the present invention are to provide such method and apparatus for target addressing and translation for data communications and to provide such method and apparatus that overcome some disadvantages of prior art arrangements.
In brief, a method and apparatus are provided for target addressing and translation in a non-uniform memory environment with user defined target tags. The apparatus for target addressing and translation includes a processor and a first address translation unit coupled to the processor. The first address translation unit translates an effective address (EA) to a real address (RA). The first address translation unit includes a target tag associated with each address translation.
In accordance with features of the invention, a second address translation unit translates a real address (RA) to a target address (TA). The second address translation unit includes a target tag associated with each address translation. A cache includes a cache directory and a target tag is stored into the cache directory with each cache fill.
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Broberg, III Robert Neal Carlton
Byrn Jonathan William
McBride Chad B.
McClannahan Gary Paul
Chace Christian P.
International Business Machines - Corporation
Kim Matthew
Pennington Joan
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