Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-04-12
2002-12-31
Wong, Don (Department: 2821)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06502224
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to a technique for synthesizing logic circuits. More specifically the present invention relates to a logic synthesis technique in which propagation delays across circuits are equalized.
2. Description of Related Art
Digital logic circuitry is becoming increasingly prevalent in all kinds of devices. Many systems that were once operated through mechanical or analog electronic means are now controlled through digital electronics. Audio technology, including both home stereo equipment and the telephone system, is increasingly dominated by digital technology. Vehicles such as airplanes and automobiles, which were once controlled largely through mechanical means, are now primarily controlled by digital computers. Digital signal processing and digital wireless communications are just now beginning to replace long-dominant analog communications technology.
Designers of digital logic circuitry today generally use synthesis tools, computer programs for deriving a low-level implementation of a logic circuit from a high-level representation of logic functions. For instance, a designer may wish to connect two D-type flip-flops in series. The designer will specify to the synthesis tool that two D-type flip-flops connected in series are desired. The synthesis tool will then select circuit schematics for the two flip-flops from a standard library and combine the schematics to derive a low-level (logic-gate level) implementation for the circuit. In many synthesis tools, a designer has the option of choosing different design goals, such as power minimization, speed optimization, and so forth, so that the schematics picked from the standard library address these goals.
These schematics can then be translated into a physical form. Methods for translating a schematic into a physical form include deriving an integrated circuit layout directly from the schematic using some sort of integrated circuit compiler, and implementing the circuit in some kind of programmable logic device (PLD).
Programmable logic devices, including programmable logic arrays (PLAs), are integrated circuits containing connected blocks of circuitry for performing basic logic functions. A circuit design is “programmed” or “burned” into a PLD by eliminating those connections between circuitry blocks that are not needed (by, for instance, blowing an internal fuse in the PLD, in the case of a “fuse-programmable” PLD) or defining certain wiring levels within the PLD (in the case of a “mask-programmable” PLD).
Conventional logic circuit synthesis techniques, however, suffer from a number of drawbacks. In complex circuits containing many signal paths, propagation delays (delays of signals through a circuit from input to output) can easily become unequal, which causes synchronization problems, particularly at high speeds.
Programmable logic arrays (PLAS), which are a type of PLD, solve the problem of synchronizing outputs, but only for simple circuits. PLAs are generally made up of arrays of AND and OR logic gates, and can be used to synthesize 2-level logic functions using a level of ANDs and a level of ORs. For simple circuits that can be implemented using a two-level AND-OR schematic, PLAs are an adequate solution, but for more complex circuits they are not.
What is needed, then, is a synthesis technique for producing circuits with synchronized outputs that is applicable for more complicated circuits, and a tool for implementing the technique.
SUMMARY OF THE INVENTION
The present invention is directed toward a method of synthesizing logic circuits having synchronized outputs, which method can be used in a synthesis tool for computer-aided engineering of logic circuits. The technique involves the a priori selection of a fixed number of logic “levels,” in which each level has a fixed propagation delay associated with it. Each level can include several logic functions, with each logic function in the level having the same propagation delay.
The logic circuit(s) to be implemented are then synthesized by connecting logic functions from one level to the next, so that every signal path must pass through each level once and only once. Logic circuits that are too complex to be synthesized using the number of levels chosen can be synthesized by partitioning the circuit into pieces that can each be synthesized using the levels available.
The physical result of such synthesis can be implemented using discrete logic components, or as a custom-fabricated integrated circuit using a standard integrated circuit compiler or layout tool, or in one or more programmable logic devices containing circuitry for each level.
REFERENCES:
patent: 5359535 (1994-10-01), Djaja et al.
patent: 5396435 (1995-03-01), Ginetti
patent: 5404311 (1995-04-01), Isoda
patent: 5636130 (1997-06-01), Salem et al.
patent: 6148434 (2000-11-01), Nozuyama
patent: 6209121 (2001-03-01), Goto
patent: 6253361 (2001-06-01), Buch
patent: 6311148 (2001-10-01), Krishnamoorthy
patent: 6317861 (2001-11-01), Hasegawa
patent: 6341363 (2002-01-01), Hasegawa
patent: 6425115 (2002-07-01), Risler et al.
Wakerly, John F., Digital Design: Principles and Practices, 2nd ed., Englewood Cliffs, NJ: Prentice Hall 1994, pp. 635-640.
Dhong Sang Hoo
Hofstee Harm Peter
Posluszny Stephen Douglas
Silberman Joel Abraham
Takahashi Osamu
Chen Shih-Chao
Nichols Michael R.
Salys Casimer K.
Wong Don
Yee Duke W.
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