Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Patent
1997-05-02
2000-10-10
Lintz, Paul R.
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
716 9, 716 12, G06F 1750
Patent
active
061311820
ABSTRACT:
A computer-based method automatically synthesizes, optimizes and compiles high performance control logic using SRCMOS LOGIC ARRAY MACROS, abbreviated as SLAMs. The method includes a series of steps that transform a high level design description into a set of SLAMs, and includes the steps of partitioning the logic description of a unit into blocks that are suitable for mapping to a target SLAM structure; mapping each logic partition to the target SLAM structure; creating a configuration and relative layout for the internal structure for each SLAM; creating an external description for each SLAM, each description being of sufficient detail to carry out physical design and integration of the unit which contains the SLAM; assembling the partitions implemented as SLAMs with other macros in the unit; resolving interface conflicts between the different macros by selecting appropriate signal interfaces for various SLAMs; repeatedly changing the external specifications of the various SLAMs; analyzing the performance of the unit; automatically compiling the schematic and layout of each SLAM within the unit based on the configuration and relative layout; and assembling the macros and analyzing the design for design rule violations.
REFERENCES:
patent: 5086477 (1992-02-01), Yu
patent: 5461577 (1995-10-01), Shaw
patent: 5801958 (1998-09-01), Dangelo et al.
Beakes Michael Patrick
Chappell Barbara Alana
Chappell Terry Ivan
Ditlow Gary S.
Dorfman Barry Lee
Do Thuan
International Business Machines - Corporation
Lintz Paul R.
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