Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2002-08-08
2004-06-01
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S097000, C327S156000, C327S172000, C375S371000
Reexamination Certificate
active
06744285
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to electrical circuits and, more particularly, to a method and an apparatus for aligning the phases of clocks of different clock domains to enable data to be transferred synchronously across the clock domains.
BACKGROUND OF THE INVENTION
It is common for integrated circuit (IC) technology to have multiple clock domains. In each clock domain, the domain logic is driven by a clock operating at a particular frequency that is different from the clock frequency of the clocks of the other clock domains. When data is transferred between clock domains, the transfer of data must be synchronized between the clock domains so that data will not be lost, so that setup and hold time violations will not occur in the downstream logic and so that the synchronization of data between clock domains will occur with maximum throughput. In order for these goals to be accomplished, many different clock domain synchronization techniques and designs have been developed.
These various synchronization solutions generally fall into two categories. The first and simplest solution is to place synchronizing flip flops at the location where transferred data is received at the receiving clock domain, as shown in FIG.
1
.
FIG. 1
illustrates logic 1 of clock domain A being controlled by clock A and logic 2 of clock domain B being controlled by clock B. Clocks A and B have different clock rates. Data sent from clock domain A to clock domain B must be synchronized to clock B and data sent from clock domain B to clock domain A must be synchronized to clock domain A. Otherwise, data transferred between clock domains A and B may be lost and/or erroneous results may occur due to setup and/or hold time violations. Data output from logic 1 is output at the rate of clock A, as indicated by line
3
and must be converted into data at clock B. Data output from logic 2 is output at the rate of clock B, as indicated by line
4
. The data being sent from logic 1 to logic 2 is received by flip flop
5
, which is controlled by clock B, as indicated. The data being sent from logic 2 to logic 1 is received by flip flop
6
, which is controlled by clock A, as indicated.
When clock B is high, data at the D input of flip flop
5
(i.e., data being transferred from logic 1 to logic 2) is output from the Q output of flip flop
5
at the clock rate of clock B so that the data is synchronized to the logic 2 of clock domain B. Similarly, when clock A is high, data at the D input of flip flop
6
is output from the Q output of flip flop
6
(i.e., data being transferred from logic 2 to logic 1) at the clock rate of clock A so that is synchronized with the logic 1 of clock domain A.
Solutions of the type shown in
FIG. 1
may not be adequate due to additional delays of the data signals and uncertainty as to when the data will arrive during a clock cycle. The second solution does not utilize the flip flop synchronizer circuit of
FIG. 1
, but rather, ensures that the data crosses the clock domains synchronously by controlling the clock skews between the clock domains. This solution, which is represented in
FIG. 2
by the transfer of data between clock domain
10
, which is being driven by clock A, and clock domain
11
, which is being driven by clock B. The solution represented by
FIG. 2
is more difficult to implement than that of FIG.
1
and depends on the clock frequencies and how they align with each other. In the past, in order to implement this solution, the designer would simulate the clock alignment as precisely as possible before releasing the design for fabrication. For example, a 5:4 ratio of the rates of clocks A and B would mean that the rising edges of both clocks align at the beginning of every fifth cycle of clock A and every fourth cycle of clock B. The IC designer would design the clock circuits so that the rising edges that occur on the fifth and fourth clock cycles of clocks A and B, respectively, are as precisely aligned as possible given the other design considerations of the IC.
The problem with the solution represented by
FIG. 2
is that, if a determination is made that the timing of the IC is off, no “quick fix” is available to check the alignment of the clocks to determine if the timing problem is due to misalignment of the clocks. Rather, schematic-based simulations must be performed to correct the alignment of the clock domains. Furthermore, if timing problems occur after fabrication of the IC, there is no way to correct the phase alignment of the clocks of the IC.
Accordingly, a need exists for a method and apparatus that enable precise data transfer across different clock domains and that enable the alignment of the phases of the clocks to be corrected after the IC has been fabricated.
SUMMARY OF THE INVENTION
The present invention provides a method and an apparatus for aligning the phases of clocks of different clock domains of an IC to enable data to be transferred synchronously across the clock domains. The present invention comprises a phase-alignment system that is adjustable via a user interface to enable the clock phases to be adjusted. A user controls the degree of alignment of the phases via the user interface. The present invention enables the phases of clocks of different clock domains to be adjusted even after the IC has been fabricated, the apparatus including phase-alignment logic which is configured to receive input from the user interface. The input automatically configures the phase-alignment logic to cause the phase of at least one of the first and second clocks to be adjusted, thereby adjusting the degree of alignment of the phases of the first and second clocks.
The method of the present invention is directed to adjusting a degree of alignment of clock phases of a first clock driving logic of a first clock domain of an integrated circuit (IC) and a second clock driving logic of a second clock domain of the IC. The method comprises the steps of receiving input from a user interface in phase-alignment logic of the IC and then automatically configuring the phase-alignment logic in accordance with the input to delay at least one of the first and second clocks in time, thereby adjusting the degree of alignment of the phases of the first and second clocks.
These and other features and advantages of the present invention will become apparent from the following description, drawings and claims.
REFERENCES:
patent: 4868513 (1989-09-01), Piercy et al.
patent: 6219395 (2001-04-01), Pollack et al.
patent: 6437620 (2002-08-01), Singor
patent: 02-220102 (1990-09-01), None
patent: 07-146642 (1995-06-01), None
Groth Cory
Mangum Wayne G.
Meier Peter J.
Miller Brian C.
Agilent Technologie,s Inc.
Tan Vibol
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