Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
1998-09-30
2001-03-27
Lee, Thomas (Department: 2182)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S400000, C709S241000
Reexamination Certificate
active
06209106
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method and apparatus for synchronizing selected logical partitions of a partitioned information handling system to an external time reference and, more particularly, to such a method and apparatus that provides a way to specify a fixed time offset from the external time reference for a group of logical partitions that make up a sysplex running on multiple central processor complexes.
2. Description of the Related Art
Many IBM S/390® and compatible hardware machines operate in what is known as logically partitioned (LPAR) mode. Logically partitioned computer systems are well known in the art and are described in U.S. Pat. No. 4,564,903 (Guyette et al.), U.S. Pat. No. 4,843,541 (Bean et al.), and U.S. Pat. No. 5,564,040 (Kubala), incorporated herein by reference. Commercial embodiments of logically partitioned systems include IBM S/390 processors with the Processor Resource/Systems Manager™ (PR/SM™) feature and are described, for example, in the IBM publication
Processor Resource/Systems Manager Planning Guide,
GA22-7236-03, June 1998, incorporated herein by reference.
Logical partitioning allows the establishment of a plurality of system images within a single physical central processor complex (CPC). Each system image is capable of operating as if it were a separate computer system. That is, each logical partition can be independently reset, initially loaded with an operating system that may be different for each logical partition, and operate with different software programs using different input/output (I/O) devices. Logical partitioning is in common use today because it provides its users with flexibility to change the number of logical partitions in use and the amount of physical system resources assigned to each partition, in some cases while the entire central processor complex continues to operate.
Currently, in a partitioned S/390 central processor complex, each logical partition has its own logical partition clock together with an epoch offset indicating the difference between the logical partition clock and a host clock. This is described in U.S. Pat. No. 5,636,373 (Glendening et al.), incorporated herein by reference. By suitable setting of its epoch offset, a particular partition may be synchronized to one clock value (e.g., a test clock value for year 2000 testing), while other partitions may be synchronized to another clock value (e.g., that of an external time reference).
While a single logical partition may thus be synchronized to a test clock value, previously an operator had to use an entire central processor complex to do year 2000 testing of a multi-member “sysplex” (i.e., containing multiple logical partitions). This was done in one of two ways in S/390 environments. For a central processor complex that did not have an external time reference (ETR) attached, the operator set the time-of-day (TOD) clock of an attached support element ahead, did a power-on reset into logically partitioned mode, and used the simulated ETR support of each logical partition operating system (e.g., the SIMETRID support of OS/390 and MVS/ESA). For a central processor complex that did have a real external time reference, the external time reference was set ahead. Neither of these alternatives, however, provided an environment where a production system could operate alongside a multi-member test sysplex that had a different time/date.
U.S. Pat. No. 5,802,354 (Kubala et al.), incorporated herein by reference, describes a method and apparatus for synchronizing selected logical partitions of a partitioned information handling system to a test datesource. As described in the patent, a system operator is presented with a display panel in which the operator may specify a set of test partitions making up a test sysplex, together with a starting test clock value, or datesource. The test clock value may be selected for year 2000 testing and may differ from the production clock value to which the non-test (production) partitions are synchronized.
Each partition designated as a test partition is synchronized to the test clock upon its next activation, while production partitions are synchronized to a production clock as in a conventional configuration. The first test partition to be newly activated is synchronized to the starting test clock value entered by the system operator. Each subsequently activated test partition, on the other hand, is synchronized to the current clock value of the previously activated test partition, which has meanwhile advanced from the starting value entered by the system operator. As a result, all of the test partitions are synchronized to a common test clock value, allowing them to interact as a true sysplex. In effect, the test partitions make up a virtual sysplex with a time and date other than that of the production sysplex.
While the system described in U.S. Pat. No. 5,802,354 represents an advance over the art, certain problems remain. Currently, in order to perform year 2000 testing on multiple CPCs, the hardware involved in the test (both the CPCs and the ETR(s)) has to be dedicated to the year 2000 test effort. One cannot not simultaneously use that hardware for current-date production sysplex work.
Also, multiple sysplexes cannot be run from the same set of CPCs and ETR(s) where the time returned from a Store Clock (STCK) instruction reflects different time zones in the different sysplexes.
SUMMARY OF THE INVENTION
In general, the present invention relates to a method and apparatus for synchronizing logical partitions of a logically partitioned machine to an external time reference (ETR) clock value. Each logical partition has a logical clock capable of being set to a specified logical clock value. In accordance with the invention, an ETR offset from the ETR clock value is specified for each of a set of selected logical partitions, and the logical clock of each of the selected logical partitions is set to a logical clock value offset from the ETR clock value by the ETR offset specified for that partition. Each logical clock may comprise a time-of-day (TOD) clock, and the ETR offsets may be specified by receiving input from a system operator.
Each selected logical partition is preferably set to its logical clock value upon being newly activated. More particularly, at activation time, each selected logical partition compares its logical clock value to the ETR clock value and resets its logical clock value to the ETR clock value if the logical clock value differs from the ETR clock value. To compare the two clock values, each partition issues a first read instruction (STCK) to the logical partition manager (i.e., to the physical machine) to read the logical clock value and issues a second read instruction (STETR) to the logical partition manager to read the ETR clock value.
The logical partition manager stores a host clock value and an epoch offset for each logical partition representing the difference between the logical clock value and the host clock value for that partition. The logical partition manager responds to the first read instruction (STCK) by arithmetically combining the host clock value with the epoch offset stored for the partition to generate the logical clock value. The logical partition manager responds to the second read instruction (STETR) by arithmetically combining the ETR clock value with the ETR offset specified for the partition to generate an offset ETR clock value that is returned to the partition.
A logical partition resets its logical clock value to the ETR clock value by issuing a set clock instruction (SCK) to the logical partition manager to set the logical clock value. The logical partition manager responds to the set clock instruction (SCK) by arithmetically combining the logical clock value with the host clock value to generate an epoch offset for the partition as the difference between the logical clock value and the host clock value.
In a preferred embodiment, the interface to the LP manager for logical partition activation includes two n
Kubala Jeffrey P.
Siegel Ira G.
Trowell Kenneth M.
International Business Machines - Corporation
Kinnaman, Jr. William A.
Lee Thomas
Mai Ri Jue
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