Method and apparatus for synchronizing clock distribution of a d

Details Method and apparatus for synchronizing clock distribution of a d Method and apparatus for synchronizing clock distribution of a d

1997-12-16

1999-12-14

Robertson, David L.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

713401, G06F 1200, H04L 700

Patent

active

060031182

ABSTRACT:
This invention discloses a novel design to solve the clock skew problems in a data processing system by using PLL circuitry inside a memory controller in combination with an adjustable delay element to provide a write clock signal, a read clock signal, and a memory clock signal for triggering the write data buffer and the read buffer of the memory controller, and the memory module respectively. The memory clock signal has a phase lead relative to the read clock signal and a phase lag relative to the write clock signal. The phase lead and the phase lag compensate for phase differences between clock signals arriving at the read data buffer and the write data buffer of the memory controller, and the memory module respectively due to phase delays resulting from the different paths for transmitting clock signals, thereby synchronizing the clock signals.

REFERENCES:
patent: 5475690 (1995-12-01), Burns et al.
patent: 5481573 (1996-01-01), Jacobowitz et al.
patent: 5815462 (1998-09-01), Konishi et al.

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