Method and apparatus for synchronization of shared memory in...

Electrical computers and digital processing systems: virtual mac – Task management or control – Process scheduling

Reexamination Certificate

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C710S108000

Reexamination Certificate

active

10354813

ABSTRACT:
Method and apparatus for synchronizing access to a memory shared among a plurality of processors is described. In one example, each of the plurality of processors includes a primary bus for communicating with the memory and a secondary bus. A synchronization block is coupled to the secondary bus of each of the plurality of processors. The synchronization block includes at least one semaphore for controlling access among the plurality of processors to at least one data segment stored within the memory.

REFERENCES:
patent: 5050072 (1991-09-01), Earnshaw et al.
patent: 5790851 (1998-08-01), Frank et al.
patent: 6105099 (2000-08-01), Freitas et al.
patent: 6353869 (2002-03-01), Ofer et al.
patent: 6892258 (2005-05-01), Williams et al.
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