Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-12-19
2000-07-04
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 11, 714 12, 714 13, 714820, 714819, 707202, 707203, G06F 1100
Patent
active
060853336
ABSTRACT:
Methods and associated apparatus for automatically synchronizing the operating code between a plurality of controllers. In a first embodiment after the spare controller is swapped into the storage subsystem, if the native controller determines that the spare controller's operating code is incompatible with the native controller's operating code, then the native controller notifies the spare controller that synchronization is required between both controllers. The native controller creates an image of its operating code including configuration parameters, and copies this "synch info" into a reserved area of cache memory. The spare controller's main CPU utilizes mirroring routines to copy the operating code and configuration parameters into a reserved area of its cache memory. After the transfer is complete, the spare controller's main CPU loads the operating code and configuration parameters into its program memory and resets itself to operate with the modified program memory. In a second embodiment, a co-processor within the spare controller updates the spare controller's operating code by executing a script. The native controller builds the script that includes the operating code, configuration parameters, and instructions to retrieve the operating code and configuration parameters from the native controller's cache memory. The spare controller's co-processor transfers the script to a reserved area in the spare controller's cache memory. The native controller requests the spare controller's co-processor to execute the script which causes the co-processor to retrieve the operating code using mirroring techniques and load the spare controller's program memory with the operating code. The co-processor sends an interrupt to the spare controller's main processor to reset the spare controller.
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DeKoning Rodney A.
Harris Dale L.
Humlicek Donald R.
Sherman John V.
Snider Timothy R.
Beausoliel, Jr. Robert W.
Bonzo Bryce P.
LSI Logic Corporation
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