Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
2001-02-28
2004-08-10
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C710S058000, C375S372000, C375S376000, C709S233000, C709S248000
Reexamination Certificate
active
06775724
ABSTRACT:
“CROSS-REFERENCE TO RELATED APPLICATIONS
The present application claims the benefit of priority to Japanese Patent Application No. 2000-052063, filed on Feb. 28, 2000, and to Japanese Patent Application No. 2000-210462 filed on Jul. 11, 2000, that are incorporated herein by reference.”
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a synchronization control method and apparatus for generating output signals of frequencies synchronized with externally input data.
2. Prior Art
In recent years, systems have become popular, which transfer isochronous data such as voice or audio data from one apparatus to another for reproduction. For example, some of these systems transfer audio data from a personal computer to a simplified player for musical performance.
To reliably operate such apparatuses dealing with the transfer of isochronous data, the frequency of an input signal must be synchronized with the frequency of a corresponding output signal in a fixed manner. That is, if isochronous data are transferred between such apparatuses in an unlocked state where there is a difference in frequency phase between them, which increases with the lapse of time so that the data may be destroyed.
A PLL (Phase Locked Loop) is known as a method for generating an output signal of a frequency synchronized with a corresponding input signal. A general PLL circuit is essentially comprised of a phase comparator for comparing the phase of an input signal with the phase of a corresponding output signal, a loop filter for smoothing an output from the comparator, and a VCO (voltage controlled oscillator) for outputting a reproduction clock having a frequency varied by an output from the filter.
Further, if a 44.1 kHz sampling clock synchronized with a 1 kHz input signal is to be generated from this input signal, a frequency dividing circuit must be provided in a feedback circuit to the phase comparator, to reduce the reproduction clock frequency of 44.1 kHz to 1 kHz.
If, however, all elements required for such a circuit are constructed of hardware, the number of elements disadvantageously increases in proportion to the number of frequency dividing stages, resulting in a complicated circuit construction. Further, if the PLL is constructed of hardware, the ratio of an input frequency to an output frequency is disadvantageously fixed, whereby input and output signals having various different frequency ratios cannot be flexibly processed.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a synchronization control apparatus and method that enables synchronization control which can flexibly accommodate various frequencies using a simple circuit construction.
To attain the above object, the present invention provides a synchronization control apparatus comprising a storage device that has a predetermined capacity for storing externally input data, a first frequency controlling device that controls an output frequency at which data stored in the storage device are output, based on an average frequency which is an average of the output frequency and on a coefficient for setting the average frequency at a fixed value, the first frequency controlling device calculating the average of the output frequency whenever a timing signal is input in accordance with a predetermined cycle and determining the coefficient depending on a free capacity of the storage device at a time of inputting of the timing signal, and a second frequency control device that operates if the calculated average frequency continuously exhibits a fixed value for a predetermined time period, to decrease the output frequency when the free capacity of the storage device is larger than a predetermined upper threshold value, while increasing the output frequency when the free capacity of the storage device is smaller than a predetermined lower threshold value, wherein the upper threshold value and the lower threshold value each comprise two different values.
Preferably, the synchronization control apparatus according to the present invention comprises a signal generating device that generates a signal of a predetermined frequency, and a frequency dividing device that divides the predetermined frequency using a frequency dividing value, and wherein the first frequency controlling device and the second frequency controlling device change the frequency dividing value of the frequency dividing device to control the output frequency.
More preferably, the second frequency controlling device decreases the output frequency by adding a predetermined value to the frequency dividing value, and increases the output frequency by subtracting the predetermined value from the frequency dividing value.
Preferably, the second frequency controlling device increases or decreases the output frequency a number of times equal to or smaller than a predetermined limit number based on the upper threshold value and the lower threshold value.
To attain the above object, the present invention further provides a synchronization control method comprising a storage step of storing externally input data in a a storage device that has a predetermined capacity, a first frequency controlling step of controlling an output frequency at which data stored in the storage device are output, by calculating, based on an average frequency which is an average of the output frequency and on a coefficient for setting the average frequency at a fixed value, the average of the output frequency whenever a timing signal is input in accordance with a predetermined cycle, and determining the coefficient depending on a free capacity of the storage device at a time of inputting of the timing signal, and a second frequency control step of decreasing, if the calculated average frequency continuously exhibits a fixed value for a predetermined period, the output frequency when the free capacity of the storage device is larger than a predetermined upper threshold value, while increasing the output frequency when the free capacity of the storage device is smaller than a predetermined lower threshold value, wherein the upper threshold value and lower threshold value each comprise two different values.
The above and other objects of the invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4961188 (1990-10-01), Lau
patent: 5359727 (1994-10-01), Kurita et al.
patent: 5572169 (1996-11-01), Iwamoto
patent: 5920842 (1999-07-01), Cooper et al.
patent: 5929711 (1999-07-01), Ito
patent: 6104326 (2000-08-01), Lee et al.
patent: 6307877 (2001-10-01), Philips et al.
patent: 6347380 (2002-02-01), Chang et al.
patent: 6449017 (2002-09-01), Chen
patent: 11274922 (1999-10-01), None
patent: 2001136064 (1999-11-01), None
patent: 2001136064 (1999-11-01), None
patent: 2001177394 (2001-06-01), None
Koseki Hitoshi
Toshitani Masafumi
A. Marquez, Esq. Juan Carlos
Casiano Angel
Fisher Esq. Stanley P.
Gaffin Jeffrey
Reed Smith LLP
LandOfFree
Method and apparatus for synchronization control for various... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for synchronization control for various..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for synchronization control for various... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3349637