Method and apparatus for supporting SDRAM memory

Details Method and apparatus for supporting SDRAM memory Method and apparatus for supporting SDRAM memory

2005-05-03

2005-05-03

Robertson, David L. (Department: 2186)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C711S154000

Reexamination Certificate

active

06889284

ABSTRACT:
A memory translation hub comprising a memory channel interface, a memory bus interface, and a command generator coupled to the memory channel interface and to the memory bus interface. The memory channel interface receives a memory control packet from a memory channel. The memory bus interface provides a memory bus. The command generator causes the memory bus interface to provide memory control signals on the memory bus responsive to the memory control packet.

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Computergram International; Intel Offers SDRAM Alternative to Rambus on Camino Chipset; Jul. 14, 1999.*
Carroll, Mark; Electronic Engineering Times; “Compaq, IBM, others seek memory alternatives for Tanner- and Merced-class systems—Intel preps Direct Rambus for servers (Intel will introduce Rambus/SDRAM translation ASICs . . . ”; Aug. 17, 1998.*
“SDRAM to Direct RDRAM”, Intel Development Forum Presentation, presentation materials (undated).*
Direct RDRAM™ 128/144-Mbit (256Kx16/18x32s), RAMBUS®, May 1999, Document DL0059, May 1999, pp. 1-62, Mountain View, California.
Rambus™ Technology Overview, DL-0040-00, Aug. 23, 1999, pp. 1-14.

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