Method and apparatus for supporting scalable coherence on...

Details Method and apparatus for supporting scalable coherence on... Method and apparatus for supporting scalable coherence on...

2011-07-19

2011-07-19

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S163000, C711SE12069

Reexamination Certificate

active

07984244

ABSTRACT:
In one embodiment, a multi-core processor having cores each associated with a cache memory, can operate such that when a first core is to access data owned by a second core present in a cache line associated with the second core, responsive to a request from the first core, cache coherency state information associated with the cache line is not updated. A coherence engine associated with the processor may receive the data access request and determine that the data is of a memory page owned by the first core and convert the data access request to a non-cache coherent request. Other embodiments are described and claimed.

REFERENCES:
patent: 5734922 (1998-03-01), Hagersten et al.
patent: 6470429 (2002-10-01), Jones et al.
patent: 2007/0121659 (2007-05-01), Pong
J. Risau, et al., “Software Controlled Cache Coherence In Shared-Memory Multiprocessors,” Sep. 20, 1996, pp. 1-19.

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