Electrical computers and digital processing systems: memory – Address formation – Address multiplexing or address bus manipulation
Reexamination Certificate
1996-08-29
2001-06-26
Verbrugge, Kevin (Department: 2185)
Electrical computers and digital processing systems: memory
Address formation
Address multiplexing or address bus manipulation
Reexamination Certificate
active
06253302
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to computer systems and computer system buses. More particularly, this invention relates to supporting multiple overlapping address spaces on a shared bus in a computer system.
2. Background
Modem computer systems typically have multiple agents coupled together via a system bus. Typically, the agents are integrated circuit chips with multiple pins coupling each agent to the bus. These agents may include, for example, a processor(s), a memory device(s), a mass storage device(s), etc. In order for the computer system to operate properly, these agents should be able to effectively communicate with each other via the bus.
Different agents in a computer system and different locations within these agents (e.g., a register or other memory location) are typically accessed via a particular address. The range of addresses which can be used by a particular agent is typically referred to as the address space of that agent. A typical range for address spaces used by modem computer systems is from 8 to 44 bits. As technology has advanced, the address space being supported by particular agents has increased in order to accommodate a wide range of agents and memory locations.
Often, newer agents support a larger address space than older agents. However, in order to increase flexibility in computer system design and provide backwards compatibility, it would be beneficial to provide a mechanism which supports smaller address spaces as well as newer, larger address spaces. The smaller and larger address spaces typically overlap. For example, the first 8-bit space of a 16-bit address space and the entire space of an 8-bit address space are the same, and thus are referred to as overlapping. Additionally, some newer agents (for example, input/output devices) may have no need to use the larger address spaces. Therefore, using additional pins on these agents in order to couple them to the bus needlessly increases the cost and physical size of the agents.
One solution to supporting multiple address spaces is to use different requests for different address spaces. For example, a request in an 8-bit address space and a request in a 16-bit address space would be two different commands, using different request lines on the bus. However, this solution greatly increases the number of control lines required on a bus, because a significant number of additional control lines is needed for each of the different address spaces which are supported. Thus, it would be beneficial to provide a mechanism for supporting different address spaces which does not require a significant number of additional control lines.
As will be described in more detail below, the present invention provides a method and apparatus for supporting multiple overlapping address spaces on a shared bus to achieve these and other desired results which will be apparent to those skilled in the art from the description that follows.
SUMMARY OF THE INVENTION
A method and apparatus for supporting multiple overlapping address paces on a shared bus is described herein. The apparatus includes both an address comparator and an address size indicator. The address comparator compares an address, corresponding to a request to be issued on the bus, to a plurality of address spaces. The address size indicator indicates a first address space of the plurality of address spaces to which the address corresponds.
According to one embodiment, the address size indicator encodes the first address space onto one or more control lines. The size of the address is then issued on the bus along with the address, thereby informing the other agents on the bus of the address space for the request.
Additionally, according to one embodiment, an agent which receives the address size indicator compares the address size to the address space(s) which it supports. If the address space is within the range supported by the agent, then the agent performs parity checking on the entire address. However, if the address space is outside the range supported by the agent, then the agent knows it is not the target of the request. Additionally, if the address space is outside the range supported by the agent, then the agent performs parity checking on only part of the address, rather than the entire address, thereby allowing the agent to identify any parity errors in that part of the address.
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MacWilliams Peter D.
Pawlowski Stephen S.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Verbrugge Kevin
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