Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2001-07-10
2003-03-04
Ellis, Kevin L. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S005000, C711S170000
Reexamination Certificate
active
06530007
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memories and memory controllers, and more specifically to computer systems having multiple memories and a memory controller.
2. Description of the Related Art
In most computer systems, microprocessors operate at a much higher speed than the related memory. Ever since the first AT-compatible computers were introduced with 80286 microprocessors, wait states have been added when the microprocessor requests information from memory. More recently, however, various methods such as page mode and static column techniques have increased memory speed substantially. Interleaving of memory, in which total RAM is divided into various banks, storing sequential bits in alternate banks, and using high-speed memory cache have also increased memory access speed.
Dynamic random access memory (DRAM) is typically organized in rows and columns, which can also help increase memory speed when the row length is such that repeated accesses are more often on the same row than between different rows. Typical DRAM configurations include 256×8, 1M×32, 2M×32, 4M×32, 1M×36, 2M×36, 4M×36, 8M×36, 1M×40, 1M×16, 256K×16, 512K×8, etc. Other options, such as whether the memory is a SIMM or DIMM, whether fast page mode is available, and what the various access times are, are all subject to selection by the board configuration engineer. By determining the number of rows and columns of organization, by the byte density, by pin count, by packaging type, access time, operating current, and the number of chips in the package, and other considerations, a board configuration engineer can select an appropriate DRAM structure for a particular system's needs.
Given the large number of options, new systems often render previous systems obsolete. Depending on the cost of the consequent upgrade requirements, an end user, customer, or consumer must decide whether to completely replace an existing system, whether to struggle along as long as possible with the existing system, or whether to attempt a partial upgrade, in which some components may be replaced with newer components. The latter alternative, which may be considered a temporary stopgap measure postponing the inevitable cost of an upgrade, however, is not typically possible. The end user is often forced either to replace the system entirely, or to struggle along with an existing system. Given the rapid development of computer systems, the consumer is therefore often left with an expensive, inevitable, and frequently recurring upgrade need.
While this can be expensive for consumers, the cost can be devastating to small, medium, and large businesses, which often have a local network of desktop computers with one or more servers. The servers can often have tens of thousands of dollars worth of memory components. Replacing all the memory in a server, therefore, can be an enormous expense. Because development in memory speeds is often revolutionary rather than evolutionary, a small business is frequently faced with the dilemma of whether to completely upgrade the system, including the server connected to the local network, or whether to struggle along with the present system.
Unfortunately, the small business has typically not been able to upgrade in small steps, since products are often configured with only a single memory type. Given the large memory requirements of most servers and other large computer systems, even a small difference in memory price between memory components, when multiplied by the large memory needs of a typical computer system, can translate into an enormous investment. Because a memory controller, regardless of whether the memory controller contains a cache, can typically only communicate with a single type of memory, the owner of the large computer system has typically been required to select a single memory speed, configuration, and other constraints.
Moreover, most computers have used a single memory module size throughout the memory array, to facilitate interleaving. Memory modules are typically slower than the processors to which they are coupled. For this reason, many computer systems require wait states during a memory access. Although the use of wait states slows a computer down, the processor always has the correct value of data. To reduce the need for wait states, interleaving of memory has often been used. Interleaving is a method of writing adjacent memory locations to different memory banks. For example, one bank may hold the odd memory locations and another bank may hold the even memory locations. When sequential memory locations are addressed, one bank can provide data access while the other is free to complete its precharge from the previous access to minimize the memory latency. However, to be fully effective, the banks should be of equal size. Using different memory bank sizes is problematic when high numbers of memory locations are addressed.
BRIEF SUMMARY OF THE INVENTION
Briefly, the present invention describes, in one embodiment, a memory controller capable of supporting heterogeneous memory configurations. Several different memory module types are coupled to a bus via the memory controller of the present invention, and communications occur seamlessly with the bus. The memory controller receives memory requests from one or more processors or other bus masters via the bus. The memory controller receives the memory request, identifies a memory, and also memory access parameters, and accesses the memory and returns the resulting data (during a read request) or stores the data (during a write request). When the memory provides the data (on a read request), to the memory controller, the memory controller provides the resulting data to the bus, where it can be read by the processor.
In some systems, the memory controller of the present invention is a two-tier memory controller system having a first memory controller coupled to the bus and to the second tier of memory controllers. Each of the memory controllers in the second tier is coupled to the first memory controller and to a single type of memory module. The first memory controller receives access requests from the bus. The first memory controller identifies a second memory controller within the second tier. If desired, memory striping may be used, to balance memory use and to prevent clumping of memory accesses within a single bank or memory module. Thus, the various memory controllers in the second tier are used approximately equally, in some embodiments, at a frequency roughly equivalent to the percentage of memory they can access. A RAM personality module (RPM), or memory controller in the second tier, is clocked by the same clock received by the first memory controller in the memory controller system. Thus, the RAM personality module can communicate data to the first memory controller according to a protocol understandable by the first memory controller. Typically, this protocol is a protocol representative of a typical clocked synchronous dynamic random access memory (SDRAM), although another protocol could be used. From the perspective of the processor bus or host bus coupled to the front end of the first memory controller, the entire memory controller system behaves as a single memory controller. From the perspective of memory, the back end of the RAM personality module is seen as a memory controller designed specifically to be configured for that memory type.
Consequently, the front end of the RAM personality module can typically be standardized across the system, compatible with the back end of the first memory controller. However, in most embodiments of the present invention, the back end of the RAM personality module differs among the controller modules in the second tier, according to the variety of the memory modules in the memory system.
REFERENCES:
patent: 6047361 (2000-04-01), Ingenio et al.
Concurrent Support of FPM, EDO and Synchronous DRAMs, IBM MicroNews, 2ndQ. 1997, pp. 26-29.
The 12C-bus and how
Heng Chai S.
Koenen David J.
Olarig Sompong Paul
Akin Gump Strauss Hauer & Feld & LLP
Compaq Information Technologies Group L.P.
Ellis Kevin L.
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