Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2001-04-17
2002-05-07
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S226000, C365S189110
Reexamination Certificate
active
06385098
ABSTRACT:
TECHNICAL FIELD
This invention relates to memory devices, and more particularly, to a method and apparatus for supplying regulated power to various components of memory devices in a manner that facilitates stress testing of the components.
BACKGROUND OF THE INVENTION
Memory devices are in common use in a wide variety of applications. For example, memory devices are used in personal computers, telephone answering machines, and cellular telephones. Various types of memory devices are commercially available, including read-only memories (“ROMs”), which may be programmable (“PROMs”), and random access memories (“RAMs”), which may be either static random access memories (“SRAMs”) or dynamic random access memories (“DRAMs”). Furthermore, there are a variety of DRAM types available, and more being developed. For example, asynchronous DRAMs, synchronous DRAMs (“SDRAMs”), and video graphics DRAMs are currently available, and Synchronous Link DRAMs (“SLDRAMs”) and RAMBUS DRAMs (“RDRAMs”) will soon be available.
Although the following discussion of problems encountered when testing conventional memory devices will focus on such problems in the context of an SDRAM, it will be understood that these or similar problems exist to varying degrees with other types of memory devices. Similarly, although the solutions to these problems using the disclosed embodiments of the invention are explained in the context of an SDRAM, it will be understood that they are applicable to other types of memory devices.
One example of a conventional SDRAM
10
exhibiting problems that can be alleviated using the disclosed embodiments of the invention is shown in FIG.
1
. The SDRAM
10
includes an address register
12
that receives either a row address or a column address on an address bus
14
. The address bus
14
is generally coupled to a memory controller (not shown in FIG.
1
). A row address is initially received by the address register
12
and applied to a row address multiplexer
18
. The row address multiplexer
18
couples the row address to a number of components associated with either of two memory banks
20
,
22
depending upon the state of a bank address bit BA forming part of the row address. Associated with each of the memory banks
20
,
22
are a respective row address latch
30
which, stores the row address, and a row decoder
32
, which applies various row signals to its respective array
20
or
22
as a function of the stored row address. The row address multiplexer
18
also couples row addresses to the row address latches
30
for the purpose of refreshing the memory cells in the arrays
20
,
22
. The row addresses are generated for refresh purposes by a refresh counter
40
, which is controlled by a refresh controller
42
.
After the row address has been applied to the address register
12
and stored in one of the row address latches
30
, a column address is applied to the address register
12
. The address register
12
couples the column address to a column address latch
50
. Depending on the operating mode of the SDRAM
10
, the column address is either coupled through a burst counter
52
to a column address buffer
56
or to the burst counter
52
which applies a sequence of column addresses to the column address buffer
56
starting at the column address output by the address register
12
. In either case, the column address buffer
56
applies a column address to a column decoder
58
, which applies various column signals to respective column circuitry
60
,
62
, each of which includes sense amplifiers and associated circuitry.
The column circuitry
60
,
62
receive data from the arrays
20
,
22
, respectively, and couple the data to a data output register
70
, which applies the data to a data bus
72
. Data to be written to one of the arrays
20
,
22
is coupled from the data bus
72
through a data input register
74
to the column circuitry
60
,
62
where it is transferred to one of the arrays
20
,
22
, respectively. A mask register
76
may be used to selectively alter the flow of data into and out of the column circuitry
60
,
62
such as by selectively masking data to be read from the arrays
20
,
22
, respectively.
The above-described operation of the SDRAM
10
is controlled by a command decoder
78
responsive to high level command signals received on a control bus
79
. These high level command signals, which are typically generated by a memory controller (not shown in FIG.
1
), are a clock enable signal CKE*, a clock signal CLK, a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, which the “*” designating the signal as active low. However, other high level command signals may be used. In either case, the command decoder
78
generates a sequence of command signals responsive to the high level command signals to carry out the function (e.g., a read or a write) designated by each of the high level command signals.
The SDRAM
10
also includes an internal voltage regulator
80
that supplies various regulated voltages, including V
PP
, V
CCR1
and V
CCR2
. V
PP
is typically a “pumped” voltage having a magnitude greater than the magnitude of an external supply voltage V
CCX
, and is used for such purposes as generating wordline voltages for the arrays
20
,
22
, and supplying power to the data output register
70
. However, a negative pumped voltage V
BB
may also be generated that is used to bias the substrate of the SDRAM
10
. The voltage V
CCR1
is typically a regulated voltage that is used to apply power to the arrays
20
,
22
, and V
CCR2
is typically a regulated voltage that is used to apply power to the other circuitry in the SDRAM
10
.
The internal voltage regulator
80
is illustrated in further detail in FIG.
2
. The voltage regulator
80
includes three internal voltage regulator circuits
90
,
92
,
94
, each of which is powered by the external power supply voltage V
CCX
. The voltage regulator circuits
90
,
92
,
94
are identical to each other, and thus have the same performance characteristics. Each of the voltage regulator circuits
90
,
92
,
94
is also coupled to a reference voltage generator
96
, which supplies the voltage regulator circuits
90
,
92
,
94
with a common reference voltage V
REF
. The design of the reference voltage circuit
96
, which has the characteristics described below, is well within the ability of one of ordinary skill in the art. Therefore, in the interests of brevity, a specific design for the reference voltage circuit
96
will not be described.
The voltage regulator circuit
90
generates a regulated voltage V
CCR1
which, as explained above, supplies power to the arrays
20
,
22
. Similarly, the voltage regulator circuit
92
generates a regulated voltage V
CCR2
,which supplies power to the other circuitry in the SDRAM
10
. Finally, the voltage regulator circuit
94
generates a regulated voltage V
CCR3
, which supplies power to conventional charge pumps
98
. The charge pumps
98
, which are generally entirely separate circuits (not shown) for each pumped supply voltage, generate a positive pumped supply voltage V
PP
, which may be used as described above, and a negative voltage V
BB
, which, as described above, is used to bias the substrate of the SDRAM
10
.
The performance characteristic of the regulator circuits
90
,
92
,
94
is shown in
FIG. 3
, in which the regulated output voltage V
CCR
is shown on the y-axis as a function of the external supply voltage V
CCX
plotted on the x-axis. As shown in
FIG. 3
, the regulated output voltage V
CCR
increases linearly with the external supply voltage V
CCX
until the regulator circuits
90
,
92
,
94
begin to regulate, which occurs at about two volts. Thereafter, the regulated output voltage V
CCR
remains constant as the external supply voltage V
CCX
continues to increase. However, the regulator circuits
90
,
92
,
94
are only capable of regulating the output voltage V
CCR
over a limited range of supply voltages. When the external supply voltage V
CCX
r
Butler Hal W.
Casper Stephen L.
Porter Stephen R.
Dorsey & Whitney LLP
Hoang Huan
Micro)n Technology, Inc.
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