Method and apparatus for supplementary command bus

Details Method and apparatus for supplementary command bus Method and apparatus for supplementary command bus

2005-04-05

2005-04-05

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189030

Reexamination Certificate

active

06876589

ABSTRACT:
An electronic system according to various aspects of the present invention includes a memory having a location-specific command interface and a general command interface. The memory communicates with other components in the system via a main command bus configured to transfer address-specific commands and a supplementary command bus configured to transfer general commands. Commands may be received by the memory simultaneously at the respective interfaces.

REFERENCES:
patent: 4426644 (1984-01-01), Neumann et al.
patent: 5319753 (1994-06-01), MacKenna et al.
patent: 5721860 (1998-02-01), Stolt et al.
patent: 5748551 (1998-05-01), Ryan et al.
patent: 5831924 (1998-11-01), Nitta et al.
patent: 6230235 (2001-05-01), Lu et al.

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