Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2011-01-25
2011-01-25
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07877713
ABSTRACT:
A method is provided to evaluate substrate noise propagation in an integrated circuit design, the method comprising: providing a tile definition that specifies an electrical model associated with instances of the tile; mapping a plurality of respective tile instances to respective locations of the substrate; obtaining respective waveforms indicative of digital switching induced power grid fluctuations associated with the respective identified contacts; and associating a voltage with a selected tile instance of the tile grid that is indicative of substrate noise injection due to waveforms associated with contacts encompassed by the selected tile instance.
REFERENCES:
patent: 5459349 (1995-10-01), Kobatake
patent: 2005/0257077 (2005-11-01), Dutta et al.
patent: 2006/0184904 (2006-08-01), Murgai et al.
patent: 2007/0156379 (2007-07-01), Kulkarni et al.
patent: 2007/0288219 (2007-12-01), Zafar et al.
patent: 2008/0072182 (2008-03-01), He et al.
patent: 2008/0093560 (2008-04-01), Puhakka et al.
patent: 2009/0006065 (2009-01-01), Kariat et al.
EDA for IC Implementation, Circuit Design, and Process Technology, Edited by L. Schaffer, L. Lavagno and G. Martin, Chapter 20, Design and Analysis of Power Supply Networks, by D. Blaauw, S. Pant, R. Chaudhry and R. Panda, pp. 20-1 to 20-14, CRC Press, 2006.
Pant, S. and Blaauw, D., Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks, University of Michigan, Ann Arbor, MI, ASP-DAC -07, Asia and South Pacific, pp. 757-762 (Jan. 2007).
Checka N., Substrate Noise Analysis and Techniques for Mitigation in Mixed-Signal RF Systems, MIT 2005.
Dharchoudhury, A., Panda, R., Blaauw, D., Valdyanathan, R., Tutulanu, B., and Bearden, D., Design and Analysis of Power Distribution networks in PowerPC Microprocessors, 1998.
Nagata, M. and Iwata, A., Substrate Crosstalk Analysis in Mixed Signal CMOS Integrated Circuits, Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific Volume , Issue , 2000 pp. 623-629.
Sato, T., Hashimoto, T., Sasagawa, R., LSI Noise Model for Power Integrity Analysis and Its Application, Fujitsu Sci. Tech. J., 42.2, p. 266-273 (Apr. 2006).
Kao, WH and Chu, WK, Noise Constraint Driven Placement for Mixed Signal Designs, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003, vol. 4, Issue , May 25-28, 2003 pp. IV-712-IV-715 vol. 4.
Cho, M., Shin, H., Pan, DZ, Fast Substrate Noise-Aware Floorplanning with Preference Directed Graph for Mixed-Signal SOCs, Proceedings of the 2006 conference on Asia South Pacific design automation, pp. 765-770.
U.S. Appl. No. 11/769,675, Non Final Office Action mailed Jan. 22, 2010, 9 pgs.
U.S. Appl. No. 11/769,675, Response filed Apr. 22, 2010 to Non Final Office Action mailed Jan. 22, 2010, 10 pgs.
U.S. Appl. No. 11/769,675 Final Office Action mailed Jul. 15, 2010, 12 pgs.
Dong Xiaopeng
Kariat Vinod
Noice David
Cadence Design Systems Inc.
Dinh Paul
Schwegman Lundberg & Woessner, P.A.
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