Method and apparatus for sub cache line access and storage allow

Details Method and apparatus for sub cache line access and storage allow Method and apparatus for sub cache line access and storage allow

1997-09-06

1998-11-10

Swann, Tod R.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

711145, 711144, G06F 1200

Patent

active

058359290

ABSTRACT:
A method and apparatus for tracking the fill status of sub cache line locations during a cache line fill operation is provided. The tracking system monitors the data cycles of a burst read during a cache line fill, and sets indicators pertaining to which of the sub cache lines within the cache line have been filled. Cache control utilizes the indicators to make those sub cache lines that have been filled available to a processing system as they are filled, rather than waiting for the entire cache line to be filled. Data is stored directly into sub cache line locations without requiring a cache line buffer.

REFERENCES:
patent: 4912631 (1990-03-01), Lloyd
patent: 5367660 (1994-11-01), Gat et al.
patent: 5586293 (1996-12-01), Baron et al.
patent: 5644752 (1997-07-01), Cohen et al.

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