Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
1999-05-24
2001-06-12
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S200000, C365S230060, C365S226000, C327S525000
Reexamination Certificate
active
06246623
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to integrated circuit memory devices, and more particularly, to a method for strobing antifuse circuits in a memory device.
BACKGROUND OF THE INVENTION
A conventional memory device is illustrated in FIG.
1
. The memory device is a synchronous dynamic random access memory (“SDRAM”)
10
that includes an address register
12
receiving either a row address and a bank address bit BA or a column address on an address bus
14
. The address bus
14
is generally coupled to a memory controller (not shown in FIG.
1
). Typically, a row address and a bank address are received by the address register
12
, and applied to a row address multiplexer
18
. The row address multiplexer
18
couples the row address to one of two row address latches
26
depending on the state of the bank address BA. Each of the row address latches
26
stores the row address and applies it to a row decoder
28
, which applies various signals to a respective memory bank array
20
,
22
as a function of the stored row address. The row address multiplexer
18
also couples row addresses to the row address latches
26
for the purpose of refreshing memory cells in the arrays
20
,
22
. The row addresses are generated for refresh purposes by a refresh counter
30
that is controlled by a refresh controller
32
. The arrays
20
,
22
are comprised of memory cells arranged in rows and columns.
After the row address has been applied to the address register
12
and stored in one of the row address latches
26
, a column address is applied to the address register
12
. The address register
12
couples the column address to a column address latch
40
. Depending on the operating mode of the SDRAM
10
, the column address is either coupled through a burst counter
42
to a column address buffer
44
, or to the burst counter
42
, which applies a sequence of column addresses to the column address buffer
44
starting at the column address output by the address register
12
. In either case, the column address buffer
44
applies a column address to a column decoder
48
, which applies various column signals to respective sense amplifiers and associated column circuits
50
,
52
for the respective arrays
20
,
22
.
Data to be read from one of the arrays
20
,
22
are coupled from the arrays
20
,
22
, respectively, to a data bus
58
through the column circuit
50
,
52
, respectively, and a read data path that includes a data output register
56
. Data to be written to one of the arrays
20
,
22
are coupled from the data bus
58
through a write data path, including a data input register
60
, to one of the column circuits
50
,
52
where they are transferred to one of the arrays
20
,
22
, respectively. A mask register
64
may be used to selectively alter the flow of data into the column circuits
50
,
52
by, for example, selectively masking data to be written to the arrays
20
,
22
.
The above-described operation of the SDRAM
10
is controlled by a control logic circuit
66
, which includes a command decode circuit
68
and a mode register
69
. The control logic circuit
66
is responsive to high level command signals received from a control bus
70
through the command decode circuit
68
. The high level command signals, which are typically generated by the memory controller, are a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*. The memory controller also typically provides a clock enable signal CKE* and a clock signal CLK through the control bus
70
to the control logic circuit
66
. The “*” designates the signal as active low. The control logic circuit
66
generates a sequence of command signals responsive to the high level command signals to carry out a function (e.g., a read or a write) designated by each of the high level command signals. The command signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of the command signals will be omitted.
Conventional memory devices such as the SDRAM
10
are tested to locate defects and failures before they are packaged. Predetermined data values are typically written to selected row and column addresses that correspond to memory cells, and voltage values are read from the memory cells to determine if the data read matches the data written to those memory cells. If the read data does not match the written data, then those memory cells are likely to contain defects which will prevent a proper operation of the SDRAM
10
.
Nearly all memory devices such as the SDRAM
10
include redundant circuitry that may be employed to replace malfunctioning memory cells found during testing. The malfunctioning memory cells may be replaced by enabling the redundant circuitry such that the memory device need not be discarded even though it contains defective memory cells. In particular, memory devices typically employ redundant rows and columns of memory cells. If a memory cell in a column or a row of a primary memory array is defective, then an entire column or row of redundant memory cells can be substituted therefore.
Substitution of one of the redundant rows or columns is accomplished in a memory device such as the SDRAM
10
by opening a specific combination of fuses, or by closing a specific combination of antifuses, in one of several fuse or antifuse banks in the SDRAM
10
. Conventional fuses are resistive devices which may be opened or broken with a laser beam or an electric current. Antifuses are capacitive devices that may be closed or blown by breaking down a dielectric layer in the antifuse with a relatively high voltage.
If the SDRAM
10
contains antifuses, a selected combination of antifuses are closed corresponding to an address of a defective row or column of cells in the SDRAM
10
. For example, if the defective row or column has an 8-bit binary address of 00100100, then the appropriate antifuses in a set of 8 antifuses are closed to store this address. The antifuses are conventionally arranged in groups of 8, each group of 8 occupying one location in an antifuse bank.
The SDRAM
10
contains several antifuse banks
90
that are located between the address latches
26
,
40
and the respective decoders
28
,
48
. The SDRAM
10
also includes a substantial number of registers
92
located in the control logic circuit
66
and in other areas of the SDRAM
10
as needed. The registers
92
are programmed with data to direct the operation of most elements in the SDRAM
10
.
When an address in the SDRAM
10
is accessed, a compare circuit compares an incoming address to addresses stored in the antifuse banks
90
to determine whether the incoming address matches an address with a defective memory cell. If the compare circuit determines such a match, then it outputs a match signal to a controller or “phase generator” in a row or column decoder
28
,
48
, respectively. In response, the row or column decoder
28
,
48
causes an appropriate redundant row or column to be accessed, and ignores the defective row or column in the array
20
,
22
.
As described above, antifuses are capacitive structures that, in their unblown states, form open circuits which may be charged to provide a corresponding rise in voltage. An antifuse may be blown by applying a relatively high voltage across it which causes the dielectric layer in the antifuse to break down and form a conductive path. Blown antifuses will conduct current while an unblown antifuse will not conduct current.
Individual antifuses are generally contained in antifuse circuits which generate a digital value or signal indicating whether the antifuse is blown or unblown. A conventional antifuse circuit
95
is illustrated in FIG.
2
. The antifuse circuit
95
receives an operating voltage Vcc at a source of a PMOS transistor
96
. The PMOS transistor
96
is coupled through two PMOS transistors
102
,
104
in parallel to an input of an inverter
106
. The input of the inverter
106
is c
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Nguyen Viet Q.
LandOfFree
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