Static information storage and retrieval – Read/write circuit – Testing
Utility Patent
1999-10-12
2001-01-02
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S205000, C365S214000
Utility Patent
active
06169696
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to semiconductor memories and, more specifically, to stress testing of such memories.
2. State of the Art
As shown in
FIG. 1
, a portion
10
of a conventional Dynamic Random Access Memory (DRAM) (not shown in its entirety) includes sense amplifiers
12
and
14
shared by a pair of sub-arrays
16
and
18
. During some read operations within the sub-array
16
, an isolation signal ISO
—
2 activates isolation NMOS transistors
20
so logic bits on bitlines
22
within the sub-array
16
can be sensed by shared sense amplifiers
12
and
14
. Meanwhile, another isolation signal ISO
—
3 deactivates isolation NMOS transistors
24
so signals on bitlines
26
within the sub-array
18
do not reach the shared sense amplifiers
12
and
14
during the read operations. Of course, some read operations in the sub-array
18
are performed in a complementary manner, with the isolation NMOS transistors
24
in an activated state and the isolation NMOS transistors
20
in a deactivated state.
As described in U.S. Pat. No. 5,339,273 to Taguchi, one method for stress testing the conventional DRAM involves reading a logic bit from one of the sub-arrays
16
and
18
, for example, while both the isolation NMOS transistors
20
and the isolation NMOS transistors
24
are activated. This loads a memory cell (not shown) outputting the logic bit with approximately twice the normal bitline capacitance C
bitline
. When the memory cell is weak, its stored charge q cannot overcome the doubled bitline capacitance C
bitline
to produce a voltage V
sense
at one of the sense amplifiers
12
and
14
that is of sufficient magnitude to be sensed (i.e., V
sense
=q÷C
bitline
, so that when C
bitline
doubles and q remains constant, V
sense
is cut in half). As a result, the logic bit may be misread, thereby identifying the memory cell as being weak. The row or column (not shown) containing the weak memory cell can then be replaced with a redundant row or column (not shown), or the DRAM can be scrapped.
Unfortunately, the Taguchi method described above does not work with sense amplifiers
28
and
30
positioned outside the sub-arrays
16
and
18
, because these amplifiers
28
and
30
are each connected to only one of the sub-arrays
16
and
18
. As a result, memory cells (not shown) connected to the sense amplifiers
28
and
30
through bitlines
32
and
34
and isolating NMOS transistors
36
and
38
(activated by isolation signals ISO
—
1 and ISO
—
4) cannot be loaded with double their normal bitline capacitance, and thus cannot be stress tested, using the described Taguchi method.
Therefore, there is a need in the art for an apparatus and method in a semiconductor memory, such as a DRAM, for stress testing memory cells associated with sense amplifiers connected to only one sub-array within the memory.
SUMMARY OF THE INVENTION
An apparatus in accordance with the present invention stress tests a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), by connecting a sense amplifier of the semiconductor memory to at least two pairs of complementary bitlines within the same memory array, such as a sub-array, of the semiconductor memory through two pairs of isolation switches activated at substantially the same time by activating circuitry of the apparatus. The apparatus thus provides for the stress testing of memory cells associated with sense amplifiers connected to only one array or sub-array within a semiconductor memory. The apparatus also provides an alternative to the conventional Taguchi method described above for stress testing memory cells associated with sense amplifiers connected to more than one array or sub-array within a semiconductor memory.
In additional embodiments of the present invention, a semiconductor memory, an electronic system, a semiconductor wafer, and a DRAM device incorporate the inventive apparatus described above.
In an inventive method for stress testing a semiconductor memory, a sense amplifier of the semiconductor memory is switchably coupled to at least two pairs of complementary bitlines in the same memory array of the semiconductor memory at substantially the same time.
REFERENCES:
patent: Re. 34718 (1994-09-01), Tobita
patent: 5298433 (1994-03-01), Furuyama
patent: 5339273 (1994-08-01), Taguchi
patent: 5367492 (1994-11-01), Kawaoto et al.
patent: 5469393 (1995-11-01), Thomann
patent: 5544108 (1996-08-01), Thomann
patent: 5726939 (1998-03-01), Cho et al.
patent: 5848017 (1998-12-01), Bissey
Britt Trask
Elms Richard
Micro)n Technology, Inc.
Nguyen Tuan T.
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