Method and apparatus for streamlined testing of electrical circu

Details Method and apparatus for streamlined testing of electrical circu Method and apparatus for streamlined testing of electrical circu

1997-06-27

1999-12-21

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714727, G01R 3128

Patent

active

060063432

ABSTRACT:
A serial scan test architecture permits complete scan test of a target circuit without requiring the test controller to interrupt its scan operation.

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Lee Whetsel, "An IEEE 1149.1 Based Logic/Signature Analyzer in a Chip", International Test Conference, Oct. 26-30. 1991.
Sridhar Narayanan, Charles Njinda and Melvin Breuer, "Optimal Sequencing of Scan Registers", IEEE, 1992, International Test Conference 1992, Paper 15.2, pp. 293-302.
"IEEE Standard Test Access Port and Boundary-Scan Architecture", Feb. 1990, pp. 1-3, 1-5, 5-5.
Samiha Mourad, "Sequential Circuit Testing", COMPCOM Spring '90 IEEE Computer Society Int'l Conference 1990, pp. 449-454.

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