Computer graphics processing and selective visual display system – Computer graphics display memory system – Addressing
Reexamination Certificate
1998-07-30
2001-10-09
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Addressing
C345S539000
Reexamination Certificate
active
06300964
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to digital image processing and more particularly to an apparatus and method for storing and retrieving digital image data in a memory for use in further processing.
BACKGROUND OF THE INVENTION
Electronic storage of digital image data prior to subsequent processing has been used for many years.
One prior art image storage method for use in systems which process multiple digital images involves using multiple image delays connected in series. Input data is fed into the first delay element, the output of the first delay element is fed into a second delay element, and so on. The outputs of all the delay elements along with the input data are then available for subsequent processing such as filtering.
Another prior art method for multiple image storage uses a large memory device (i.e. memory array) with enough storage locations (addresses) for two or more images. Image data is stored sequentially in the memory array, and retrieved at a later time for downstream processing. This method requires multiple read operations to retrieve all of the desired data from each of the individual images stored in the memory array. Multiple read operations require a very high speed and costly memory array and additional logic circuits to control the reading from multiple addresses.
As discussed above, prior art methods have been used in downstream image processing applications. One such application involves converting a series of film frames to video. To convert a 24 Hz film to 60 Hz interlaced video, the individual film frames are first scanned and separated into two video fields (A and B). Unlike live video, these two fields are not temporally displaced; fields A and B can be displayed in either order as they both contain material captured at the same time. Following this step, the film fields are displayed one after the other, alternating between A and B with an extra field inserted every four fields. This process is called 3:2 pulldown, so named for the number of video fields “pulled down” from each film frame (three fields from Frame
1
, two fields from Frame
2
, etc.). The resulting field rate becomes 60 Hz which can be easily transferred to videotape.
The prior art techniques discussed above do not allow for variations in the input data rate without affecting the output image processing rate. It is well understood that variations in data rates are common in video and graphics sources, especially if the original source is in an analog format (such as a VCR) or communicated over a bus. In addition, the prior art techniques result in a delay between input and output which is an integral number of image delays. In some cases it is desirable to have a non-integral or variable amount of delay between input and output, such as in temporal filtering between multiple images or in frame rate conversion, as discussed above. Furthermore, in some circumstances minimum latency from input to output may be required.
The following prior art is considered pertinent to the present disclosure:
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Roskowski, et al
video and graphics signals in a
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5,550,592 -
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5,598,525 - Nally, et al.
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SUMMARY OF THE INVENTION
According to the present invention, a more flexible solution is provided to image processing than is provided in the prior art where the output image is a function of one or more input images, such as in video de-interlacing, frame rate conversion, temporal filtering and interpolation, and image motion analysis. A storage technique is provided for multi-image processing where it is desired to have a non-integral number of image delays between input and output, or where the amount of delay between input and output is required to be variable over time; and where the image data is not required to be transferred serially along the sequence of image delays.
According to another aspect of the present invention, an improvement is provided in digital image storage for downstream processing of a 3:2 pulldown sequence of video. The invention provides techniques for storing the images in such a way as to allow processing of images originating only from a specific film frame while storing incoming data from a different film frame for future processing. The aforementioned benefits of the present invention, namely a non-integral or variable amount of delay between input and output, also apply in the storage of a 3:2 pulldown sequence of video.
Therefore, in accordance with the present invention there is provided an image data storage and retrieval device using a memory array which is partitioned into at least two sections. A write pointer is used to generate addresses of the memory (including all sections of the memory) where image data is to be stored. A write mask generator is used to mask predetermined sections of the memory addressed by the pointer where it is desired to prevent overwriting of data. A read pointer generates addresses in the memory array from which data is to be retrieved for further processing.
The method of operation for storing the input data according to the present invention comprises in its most general aspect the steps of:
1) Generating a write pointer to indicate the location in the memory array where new input data is to be stored;
2) Generating a write mask which inhibits writing to sections of the memory array, so that stored data from other images is not overwritten;
3) Enabling the writing of the input data into the array.
4) Following completion of the input image data, the write pointer may be reset if old data is to be overwritten, or unmodified if new data is to be stored in a separate address space within the memory array.
Concurrently with the storage of input data, the method of operation for retrieving the output data comprises the steps of:
1) Generating a read pointer to indicate the location in the memory array where the desired image data to process is located;
2) Enabling the reading of the stored data from the array, with the ability to access all corresponding image data in all stored images simultaneously.
3) Following completion of the output image data, the read pointer is reset to the location where the next image data is stored. This may be the same location as the data previously read or a new location where newer data is stored.
In one more aspect of the present invention, the storage for image data is comprised of multiple memory arrays wherein writing to each individual array can be selectively controlled through use of array enable signals, in lieu of a write mask with a single memory array.
In a further aspect of the present invention, the storage for image data may be contained on the same device as the image processing circuits.
In a still further aspect of the present invention, the memory array utilizes a single bidirectional data bus for both writing data to the memory array and also reading data from the memory array. This aspect is shown in FIG.
8
A.
In yet one more aspect of the present invention, the memory array utilizes a single unified address input to indicate both reading and writing locations along with an additional input indicating whether the address indicates a write location or a read location, and a unified address generator which supplies
Genesis Microship, Inc.
Staas & Halsey , LLP
Tung Kee M.
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