Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
1998-02-27
2001-02-27
Picardat, Kevin M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S529000, C365S096000, C365S225700, C438S014000, C438S131000
Reexamination Certificate
active
06194738
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuit test circuits and methods. The invention is particularly related to semiconductor memory devices having internal test circuits, and methods of testing semiconductor memory devices.
BACKGROUND OF THE INVENTION
Semiconductor integrated circuit devices are manufactured on a thin wafer of semiconductor material. Generally many devices are manufactured on a single wafer. These devices may be tested with electrical probes to verify functionality of the devices prior to singulation and/or packaging of individual devices. After a device is packaged, further tests are performed. Devices which do not receive a conventional device package may be tested in a temporary package or die holder, and later shipped in die form. Devices which are shipped in die form after passing a complete test flow may be termed Known Good Die (KGD). Some electrical tests may be performed in a Burn-In oven to weed out parts that would likely fail within a short period of time after being sold if the Burn-In step was not performed. In addition to Probe and Burn-In, parts may be tested both hot and cold to verify functionality over specified environmental conditions.
A complete test flow will often require that parts move from one piece of test equipment to another. A first piece of test equipment and test fixtures may be utilized for Probe, another for Burn-In, and yet another for packaged part testing after Burn-In. After being tested on a particular piece of test equipment, the parts may be sorted into bins according to the test results. Occasionally a part may be misbinned i.e., placed in an incorrect bin. This may occur as a result of machine malfunction, or human error. A failed part that is incorrectly placed in a passing bin has the potential of completing the test flow without further failures and may then be sold as a fully functional part.
SUMMARY OF THE INVENTION
An integrated circuit device has nonvolatile memory elements which are programmed to reflect successful completion of a test or series of tests, or completion of a formation step or a series of formation steps of a semiconductor process. Prior to peforming additional tests, the nonvolatile memory element corresponding to successful completion of a previous test is read to verify that the part has indeed successfully completed the previous test. The nonvolatile memory elements may also be read prior to performing other production related activities such as packaging the device, and performing quality assurance checks. The nonvolatile memory elements may also be read prior to sale of the devices, and in the event that a device is returned from a customer. The integrated circuit may be a memory device such as a Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Video Random Access Memory (VRAM), etc. The invention is also applicable to other types of integrated circuit devices such as microprocessors, microcontrollers, memory controllers, Application Specific Integrated Circuits (ASICs), etc. Generally, any integrated circuit which requires multiple test steps and in which a nonvolatile memory element can be incorporated without prohibitively increasing the device manufacturing cost is a candidate for incorporation of the invention.
Large volumes of data may be recorded in the process of testing a single integrated circuit device. It is not feasible to store all of this information on the device itself. In accordance with the present invention, an antifuses is blown at predetermined test milestones to record a successful completion of tests associated with the milestone. Devices which do not successfully pass the tests do not have the fuse blown. Subsequent testing of each memory chip proceeds after verification of the blown fuse indicating that the device has passed previous test procedures. Memory devices which do not pass the tests or which do not have the fuse blown are removed from the test flow.
In an alternate embodiment of the present invention, multiple fuses are used to store information concerning the results of a test process. For example, three nonvolatile memory elements may be used to store one of eight bin numbers each of which represent a part classification based on the test results.
Nonvolatile memory elements associated with test results may be used by customers as part of their incoming inspection process. The data stored in these elements may represent standard test results, or results of tests that are specific to the customer.
After initial testing, devices which pass the tests are sent to a memory device assembly area to be packaged. Some devices may not require packaging as they may be destined to be shipped in die form as Known Good Die (KGD) devices.
Prior to encapsulation, nonvolatile memory elements may be read to verify that previous test sequences have been successfully completed. After packaging, the memory devices are tested further. Device Burn-in and other test procedures are performed to verify functionality of the devices after packaging and in adverse environmental conditions. These tests are also useful in detecting devices which are subject to infant mortality. In a preferred embodiment of the invention, devices which pass some or all of these remaining tests have antifuses which are associated with post packaging test milestones. These antifuses are programmed by application of electrical signals to device inputs and/or outputs. As a final inspection prior to shipping the devices, all appropriate fuses may be read to verify successful completion of all test procedures. While certain test procedures are described such as probe testing, Burn-In, etc., it should be noted that the invention is not limited to test flows which utilize these procedures. Alternate test flows in which some or all of these tests are not performed, in which additional tests are performed, or in which multiple tests are combined into a single test are equally valid. Furthermore, nonvolatile memory elements other than antifuses may be used to store the test or formation data.
REFERENCES:
patent: 5110754 (1992-05-01), Lowrey et al.
patent: 5235550 (1993-08-01), Zagar
patent: 5301143 (1994-04-01), Ohri et al.
patent: 5345110 (1994-09-01), Renfro et al.
patent: 5352945 (1994-10-01), Casper et al.
patent: 5424652 (1995-06-01), Hembree et al.
patent: 5428311 (1995-06-01), McClure
patent: 5440240 (1995-08-01), Wood et al.
patent: 5563832 (1996-10-01), Kagami
patent: 5590069 (1996-12-01), Levin
patent: 5617366 (1997-04-01), Yoo
patent: 5619469 (1997-04-01), Joo
Micron Technology, Inc.,Quality Reliability Handbook, 1995, entire book.
Beigel Kurt
Cutter Douglas J.
Debenham Brett
Ho Fan
Luong Dien
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Picardat Kevin M.
LandOfFree
Method and apparatus for storage of test results within an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for storage of test results within an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for storage of test results within an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2563320