Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data... – Inhibiting timing generator or component
Patent
1998-07-31
2000-02-01
Heckler, Thomas M.
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
Inhibiting timing generator or component
G06F 110
Patent
active
060215062
ABSTRACT:
A method and apparatus for stopping a bus clock when there are no activities present on a bus. In the illustrated embodiment, an AGP bus couples a graphics controller to core logic to transfer data between the two devices. A controller generates a first (AGP bus) clock signal CLK and a second (internal) clock signal iclk for the first and second devices. If the controller determines that there are no graphics activities on the AGP bus (i.e., the bus is idle), the controller issues a stop request to stop the internal clock signal iclk. The processing of the stop request is delayed for a period of seven cycles on the AGP bus clock CLK to await for an objection from either the graphics controller or the core logic. If an objection is received during the seven cycle delay, the internal clock iclk will not be stopped, and will continue to run. However, if an objection is not received, then the internal clock iclk will stop. If the graphics controller is in a low power or "sleep" state, the AGP bus clock CLK is stopped, thereby conserving power.
REFERENCES:
patent: 5392437 (1995-02-01), Matter et al.
patent: 5638083 (1997-06-01), Margeson
patent: 5799198 (1998-08-01), Fung
Cho Sung Soo
Homayoun Nima
Heckler Thomas M.
Intel Corporation
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